c8051f410 Silicon Laboratories, c8051f410 Datasheet - Page 128

• Manufacturer Part Number: c8051f410
• Description: 2.0 V, 32/16 Kb Flash, Smartclock, 12-bit Adc
• Manufacturer: Silicon Laboratories

C8051F410/1/2/3
15.1. Power-On Reset
During power-up, the device is held in a reset state and the RST pin is driven low until V
settles above
DD
V
. An additional delay occurs before the device is released from reset; the delay decreases as the V
RST
DD
ramp time increases (V
ramp time is defined as how fast V
ramps from 0 V to V
). Figure 15.2 plots
DD
DD
RST
the power-on and V
monitor reset timing. For valid ramp times (less than 1 ms), the power-on reset
DD
delay (T
) is typically less than 0.3 ms.
PORDelay
Note: The maximum V
ramp time is 1 ms; slower ramp times may cause the device to be released from
DD
reset before V
reaches the V
level.
DD
RST
On exit from a power-on reset, the PORSF flag (RSTSRC.1) is set by hardware to logic 1. When PORSF is
set, all of the other reset flags in the RSTSRC Register are indeterminate (PORSF is cleared by all other
resets). Since all resets cause program execution to begin at the same location (0x0000), software can
read the PORSF flag to determine if a power-up was the cause of reset. The contents of internal data
memory should be assumed to be undefined after a power-on reset. The V
monitor is disabled following
DD
a power-on reset.
VD D
V
R S T
1.0
t
/R S T
Logic H IG H
T
P O R D e la y
Logic LO W
VD D
Pow er-O n
M onitor
R eset
R eset
Figure 15.2. Power-On and V
Monitor Reset Timing
DD
128
Rev. 1.0