c8051f410 Silicon Laboratories, c8051f410 Datasheet - Page 184

• Manufacturer Part Number: c8051f410
• Description: 2.0 V, 32/16 Kb Flash, Smartclock, 12-bit Adc
• Manufacturer: Silicon Laboratories

C8051F410/1/2/3
184
Bit 7:
Bit 6:
Bit 5:
Bit 4:
Bit 3:
Bit 2:
Bit 1:
Bit 0:
RTC0EN MCLKEN OSCFAIL RTC0TR RTC0AEN
R/W
Bit7
Note: This register is not an SFR. It can only be accessed indirectly through RTC0ADR and RTC0DAT.
Internal Register Definition 20.4. RTC0CN: smaRTClock Control
RTC0EN: smaRTClock Enable Bit.
0: smaRTClock bias and crystal oscillator disabled. smaRTClock is powered from V
1: smaRTClock bias and crystal oscillator enabled. smaRTClock can switch to the backup
battery if V
MCLKEN: smaRTClock Missing Clock Detector Enable Bit.
When enabled, the smaRTClock missing clock detector sets the OSCFAIL bit if the smaRT-
Clock clock frequency falls below approximately 20 kHz.
0: smaRTClock missing clock detector disabled.
1: smaRTClock missing clock detector enabled.
OSCFAIL: smaRTClock Clock Fail Flag.
Set by hardware when a missing clock detector timeout occurs. When the smaRTClock
Interrupt is enabled, setting this bit causes the CPU to vector to the smaRTClock interrupt
service routine. This bit is not automatically cleared by hardware.
RTC0TR: smaRTClock Timer Run Control.
0: smaRTClock timer holds its current value.
1: smaRTClock timer increments every smaRTClock clock period.
RTC0AEN: smaRTClock Alarm Enable.
0: smaRTClock alarm events disabled.
1: smaRTClock alarm events enabled.
ALRM: smaRTClock Alarm Event Flag.
Set by hardware when the smaRTClock timer value is greater than or equal to the value of
the ALARMn registers. When the smaRTClock Interrupt is enabled, setting this bit causes
the CPU to vector to the smaRTClock interrupt service routine. This bit is not automatically
cleared by hardware.
RTC0SET: smaRTClock Set Bit.
Writing a ‘1’ to this bit causes the 47-bit value in CAPTUREn registers to be transferred to
the smaRTClock timer. This bit is automatically cleared by hardware once the transfer is
complete.
RTC0CAP: smaRTClock Capture Bit.
Writing a ‘1’ to this bit causes the 47-bit smaRTClock timer value to be transferred to the
CAPTUREn registers. This bit is automatically cleared by hardware once the transfer is
complete.
R/W
Bit6
DD
fails.
R/W
Bit5
R/W
Bit4
Rev. 1.0
R/W
Bit3
ALRM
R/W
Bit2
RTC0SET RTC0CAP Variable
R/W
Bit1
R/W
Bit0
smaRTClock
Reset Value
DD
Address:
0x06
only.