c8051f410 Silicon Laboratories, c8051f410 Datasheet - Page 268

• Manufacturer Part Number: c8051f410
• Description: 2.0 V, 32/16 Kb Flash, Smartclock, 12-bit Adc
• Manufacturer: Silicon Laboratories

C8051F410/1/2/3
D
Revision 0.7 to Revision 0.8
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Revision 0.8 to Revision 1.0
•
•
•
•
•
•
268
OCUMENT
Updated specification tables with most recently available characterization data.
Corrected references to configuring pins for Analog Mode - Port Latch must contain a '1'.
SFR Definition 5.6: Address correction to 0xBA.
Added Figure 8.2 showing power connection diagram without using on-chip regulator.
Section 9
Table 11.2 : Corrected SFR Name P2MDIN on location 0xF3.
Section 14
Section 18
last sentence.
Section 19.2.2
Section 19.3
quencies.
Section 21
Table 21.4 : Made corrections to SMBus state descriptions.
Figure 24.6 : Corrected T2RCLK Mux selection options.
Figure 24.9 : Corrected T3RCLK Mux selection options.
C2 Register Definition 26.2 : Corrected DEVICEID value to 0x0C.
Updated specification tables with full characterization data.
Updated Flash write and erase procedures to include a write to FLSCL.3-0.
Changed /RST pin comments in Table 4.1, “Pin Definitions for the C8051F41x,” on page 41 for the recom-
mended pull-up resistor.
Changed the reset value of the SFR Definition 16.3. FLSCL: Flash Scale.
Removed the "Optional GND Connection" from Figure 4.5. ’Typical QFN-28 Landing Diagram’ on page 48.
Added a note regarding the maximum SYSCLK frequency to SFR Definition 19.4. CLKMUL: Clock Multi-
plier Control.
: Removed references to "High Speed Analog Mode".
, Important Note on page 151 : Added "and have the same behavior as P0 in Normal Mode." to
: Corrected SMBus maximum rate to 1/20th system clock.
: Corrected operational description of CRC engine.
: Added Figure 19.3 and text to describe behavior of clock multiplier with slower input fre-
C
: Inserted Step 3 "Release the crystal pins by writing ‘1's to the port latch."
HANGE
L
IST
Rev. 1.0