c8051f410 Silicon Laboratories, c8051f410 Datasheet - Page 167

• Manufacturer Part Number: c8051f410
• Description: 2.0 V, 32/16 Kb Flash, Smartclock, 12-bit Adc
• Manufacturer: Silicon Laboratories

Bit7:
Bit6:
Bit5:
Bits4–3: UNUSED. Read = 00b, Write = don't care.
Bits2–0: IFCN2–0: Internal Oscillator Frequency Control Bits.
Bit7:
Bits 6–0: OSCICL: Internal Oscillator Calibration Register.
IOSCEN
R/W
Bit7
Bit7
R
-
IOSCEN: Internal Oscillator Enable Bit.
0: Internal Oscillator Disabled.
1: Internal Oscillator Enabled.
IFRDY: Internal Oscillator Frequency Ready Flag.
0: Internal Oscillator is not running at programmed frequency.
1: Internal Oscillator is running at programmed frequency.
SUSPEND: Internal Oscillator Suspend Enable Bit.
Setting this bit to logic 1 places the internal oscillator in SUSPEND mode. The internal oscil-
lator resumes operation when one of the SUSPEND mode awakening events occur.
000: SYSCLK derived from Internal Oscillator divided by 128 (default).
001: SYSCLK derived from Internal Oscillator divided by 64.
010: SYSCLK derived from Internal Oscillator divided by 32.
011: SYSCLK derived from Internal Oscillator divided by 16.
100: SYSCLK derived from Internal Oscillator divided by 8.
101: SYSCLK derived from Internal Oscillator divided by 4.
110: SYSCLK derived from Internal Oscillator divided by 2.
111: SYSCLK derived from Internal Oscillator divided by 1.
UNUSED. Read = 0. Write = don’t care.
This register determines the internal oscillator period. On C8051F41x devices, the reset
value is factory calibrated to generate an internal oscillator frequency of 24.5 MHz.
SFR Definition 19.2. OSCICL: Internal Oscillator Calibration
IFRDY
SFR Definition 19.1. OSCICN: Internal Oscillator Control
R/W
Bit6
Bit6
R
SUSPEND
R/W
Bit5
R/W
Bit5
R/W
Bit4
Bit4
R
-
OSCICL
Rev. 1.0
R/W
Bit3
Bit3
R
-
IFCN2
R/W
Bit2
R/W
Bit2
C8051F410/1/2/3
IFCN1
R/W
Bit1
R/W
Bit1
SFR Address:
SFR Address:
IFCN0
R/W
Bit0
R/W
Bit0
0xB2
11000000
Reset Value
0xB3
Reset Value
Varies
167