c8051f410 Silicon Laboratories, c8051f410 Datasheet - Page 51

• Manufacturer Part Number: c8051f410
• Description: 2.0 V, 32/16 Kb Flash, Smartclock, 12-bit Adc
• Manufacturer: Silicon Laboratories

5.
The ADC0 subsystem for the C8051F41x consists of an analog multiplexer (AMUX0) with 27 total input
selections, and a 200 ksps, 12-bit successive-approximation-register ADC with integrated track-and-hold,
programmable window detector, and hardware accumulator. The ADC0 subsystem has a special Burst
Mode which can automatically enable ADC0, capture and accumulate samples, then place ADC0 in a low
power shutdown mode without CPU intervention. The AMUX0, data conversion modes, and window detec-
tor are all configurable under software control via the Special Function Registers shown in Figure 5.1.
ADC0 inputs are single-ended and may be configured to measure P0.0-P2.7, the Temperature Sensor out-
put, V
(ADC0CN) is set to logic 1, or when performing conversions in Burst Mode. ADC0 is in low power shut-
down when AD0EN is logic 0 and no Burst Mode conversions are taking place.
5.1.
AMUX0 selects the input channel to the ADC. Any of the following may be selected as an input: P0.0-P2.7,
the on-chip temperature sensor, the core power supply (V
and all signals measured are with respect to GND. The ADC0 input channels are selected using the
ADC0MX register as described in SFR Definition 5.1.
Important Note About ADC0 Input Configuration: Port pins selected as ADC0 inputs should be config-
ured as analog inputs and should be skipped by the Digital Crossbar. To configure a Port pin for analog
input, set to ‘0’ the corresponding bit in register PnMDIN (for n = 0,1,2) and write a ‘1’ in the corresponding
Port Latch register Pn (for n = 0,1,2). To force the Crossbar to skip a Port pin, set to ‘1’ the corresponding
bit in register PnSKIP (for n = 0,1,2). See
configuration details.
DD
12-Bit ADC (ADC0)
Analog Multiplexer
, or GND with respect to GND. ADC0 is enabled when the AD0EN bit in the ADC0 Control register
P0.0
P0.7
P1.0
P1.7
P2.0
P2.7
Temp Sensor
VDD
GND
27-to-1
AMUX
Figure 5.1. ADC0 Functional Block Diagram
ADC0MX
P2.3-P2.6 available on
‘F410/2
25 MHz Max
Burst Mode
Oscillator
Conversion
SYSCLK
Section “18. Port Input/Output” on page 147
Start
Rev. 1.0
Burst Mode
ADC0TK
Logic
ADC0CF
DD
ADC
12-Bit
SAR
), or ground (GND). ADC0 is single-ended
ADC0GTH ADC0GTL
ADC0LTH
VDD
ADC0CN
C8051F410/1/2/3
ADC0LTL
Conversion
Start
00
01
10
11
32
for more Port I/O
Accumulator
AD0WINT
Compare
Window
AD0BUSY (W)
Timer 3 Overflow
CNVSTR Input
Timer 2 Overflow
Logic
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