c8051f410 Silicon Laboratories, c8051f410 Datasheet - Page 166

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c8051f410

Manufacturer Part Number
c8051f410
Description
2.0 V, 32/16 Kb Flash, Smartclock, 12-bit Adc
Manufacturer
Silicon Laboratories
Datasheet

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C8051F410/1/2/3
19.1.1. Internal Oscillator Suspend Mode
When software writes a logic 1 to SUSPEND (OSCICN.5), the internal oscillator is suspended. If the sys-
tem clock is derived from the internal oscillator, the input clock to the peripheral or CIP-51 will be stopped
until one of the following events occur:
When one of the internal oscillator awakening events occur, the internal oscillator, CIP-51, and affected
peripherals resume normal operation, regardless of whether the event also causes an interrupt. The CPU
resumes execution at the instruction following the write to SUSPEND.
166
Port 0 Match Event.
Port 1 Match Event.
Comparator 0 enabled and output is logic 0.
Comparator 1 enabled and output is logic 0.
smaRTClock Oscillator Fail Event.
smaRTClock Alarm Event.
Rev. 1.0

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