c8051f410 Silicon Laboratories, c8051f410 Datasheet - Page 237

• Manufacturer Part Number: c8051f410
• Description: 2.0 V, 32/16 Kb Flash, Smartclock, 12-bit Adc
• Manufacturer: Silicon Laboratories

Bit7:
Bit6:
Bit5:
Bit4:
Bit3:
Bit2:
Bits1–0: SCA1–SCA0: Timer 0/1 Prescale Bits.
T3MH
R/W
Bit7
T3MH: Timer 3 High Byte Clock Select.
This bit selects the clock supplied to the Timer 3 high byte if Timer 3 is configured in split 8-
bit timer mode. T3MH is ignored if Timer 3 is in any other mode.
0: Timer 3 high byte uses the clock defined by the T3XCLK bit in TMR3CN.
1: Timer 3 high byte uses the system clock.
T3ML: Timer 3 Low Byte Clock Select.
This bit selects the clock supplied to Timer 3. If Timer 3 is configured in split 8-bit timer
mode, this bit selects the clock supplied to the lower 8-bit timer.
0: Timer 3 low byte uses the clock defined by the T3XCLK bit in TMR3CN.
1: Timer 3 low byte uses the system clock.
T2MH: Timer 2 High Byte Clock Select.
This bit selects the clock supplied to the Timer 2 high byte if Timer 2 is configured in split 8-
bit timer mode. T2MH is ignored if Timer 2 is in any other mode.
0: Timer 2 high byte uses the clock defined by the T2XCLK bit in TMR2CN.
1: Timer 2 high byte uses the system clock.
T2ML: Timer 2 Low Byte Clock Select.
This bit selects the clock supplied to Timer 2. If Timer 2 is configured in split 8-bit timer
mode, this bit selects the clock supplied to the lower 8-bit timer.
0: Timer 2 low byte uses the clock defined by the T2XCLK bit in TMR2CN.
1: Timer 2 low byte uses the system clock.
T1M: Timer 1 Clock Select.
This select the clock source supplied to Timer 1. T1M is ignored when C/T1 is set to logic 1.
0: Timer 1 uses the clock defined by the prescale bits, SCA1-SCA0.
1: Timer 1 uses the system clock.
T0M: Timer 0 Clock Select.
This bit selects the clock source supplied to Timer 0. T0M is ignored when C/T0 is set to
logic 1.
0: Counter/Timer 0 uses the clock defined by the prescale bits, SCA1-SCA0.
1: Counter/Timer 0 uses the system clock.
These bits control the division of the clock supplied to Timer 0 and Timer 1 if configured to
use prescaled clock inputs.
Note: External clock divided by 8 is synchronized with
the system clock.
SCA1
T3ML
0
0
1
1
R/W
Bit6
SCA0
SFR Definition 24.3. CKCON: Clock Control
0
1
0
1
T2MH
R/W
Bit5
System clock divided by 12
System clock divided by 48
External clock divided by 8
System clock divided by 4
T2ML
R/W
Bit4
Prescaled Clock
Rev. 1.0
T1M
R/W
Bit3
T0M
R/W
Bit2
C8051F410/1/2/3
SCA1
R/W
Bit1
SFR Address:
SCA0
R/W
Bit0
0x8E
00000000
Reset Value
237