c8051f410 Silicon Laboratories, c8051f410 Datasheet - Page 60

• Manufacturer Part Number: c8051f410
• Description: 2.0 V, 32/16 Kb Flash, Smartclock, 12-bit Adc
• Manufacturer: Silicon Laboratories

C8051F410/1/2/3
60
Bits7-3:
Bits2-1:
Bit0:
R/W
Bit7
AD0SC4-0: ADC0 SAR Conversion Clock Period Bits.
SAR Conversion clock is derived from FCLK by the following equation, where AD0SC refers
to the 5-bit value held in bits AD0SC4-0. SAR Conversion clock requirements are given in
Table 5.3.
BURSTEN = 0: FCLK is the current system clock.
BURSTEN = 1: FCLK is a maximum of 25 MHz, independent of the current system clock.
*Note: Round the result up.
AD0RPT1-0: ADC0 Repeat Count.
Controls the number of conversions taken and accumulated between ADC0 End of
Conversion (ADCINT) and ADC0 Window Comparator (ADCWINT) interrupts. A convert
start is required for each conversion unless Burst Mode is enabled. In Burst Mode, a single
convert start can initiate multiple self-timed conversions. Results in both modes are
accumulated in the ADC0H:ADC0L register. When AD0RPT1-0 are set to a value other
than '00', the AD0LJST bit in the ADC0CN register must be set to '0' (right justified).
00: 1 conversion is performed.
01: 4 conversions are performed and accumulated.
10: 8 conversions are performed and accumulated.
11: 16 conversions are performed and accumulated.
RESERVED. Read = 0b; Must write 0b.
AD0SC
R/W
Bit6
SFR Definition 5.2. ADC0CF: ADC0 Configuration
=
------------------- - 1
CLK
AD0SC
FCLK
R/W
Bit5
SAR
–
*
R/W
Bit4
or
Rev. 1.0
R/W
Bit3
CLK
SAR
R/W
Bit2
=
AD0RPT
----------------------------
AD0SC
FCLK
R/W
Bit1
+
1
Reserved 11111000
R/W
Bit0
SFR Address:
Reset Value
0xBC