c8051f410 Silicon Laboratories, c8051f410 Datasheet - Page 142

• Manufacturer Part Number: c8051f410
• Description: 2.0 V, 32/16 Kb Flash, Smartclock, 12-bit Adc
• Manufacturer: Silicon Laboratories

C8051F410/1/2/3
16.5. Flash Read Timing
On reset, the C8051F41x Flash read timing is configured for operation with system clocks up to 25 MHz. If
the system clock will not be increased above 25 MHz, then the Flash timing registers may be left at their
reset value.
For every Flash read or fetch, the system provides an internal Flash read strobe to the Flash memory. The
Flash read strobe lasts for one or two system clock cycles, based on FLRT (FLSCL.4). If the system
clock is greater than 25 MHz, the FLRT bit must be set to logic 1 , otherwise data read or fetched from
Flash may not represent the actual contents of Flash.
When the Flash read strobe is asserted, Flash memory is active. When it is de-asserted, Flash memory is
in a low power state. The Flash read strobe does not need to be asserted for longer than 80 ns in order for
Flash reads and fetches to be reliable. For system clocks greater than 12.5 MHz (but less than 25 MHz),
the Flash read strobe width is limited by the system clock period. For system clocks less than 12.5 MHz,
the Flash read strobe is limited by a programmable one shot with a default period of 80 ns (1/12.5 MHz).
This is a power saving feature that is very beneficial for very slow system clocks (e.g. 32.768 kHz where
the system clock period is greater than 30,000 ns).
For additional power savings, the one shot can be programmed to values less than 80 ns. The one shot
can be trimmed according the equation in the ONESHOT register description in Figure 16.4. The one shot
period must not be programmed less than the minimum read cycle time specified in Table 16.2.
The recommended procedure for updating FLRT or the ONESHOT period is:
142
Bits7–5: RESERVED. Read = 000b. Must Write 000b.
Bit 4:
Bits3–0: RESERVED. Must Write 0000b.
Reserved Reserved Reserved
R/W
Bit7
Step 1. Select SYSCLK to 25 MHz or less.
Step 2. Disable the prefetch engine (PFEN = ‘0’ in PFE0CN register).
Step 3. Clear FLRT to ‘0’ (FLSCL register).
Step 4. Set the ONESHOT period bits.
Step 5. Set FLRT to ‘1’ if SYSCLK > 25 MHz.
Step 6. Enable the prefetch engine (PFEN = ‘1’ in PFE0CN register).
FLRT: Flash Read Time Control.
This bit should be programmed to the smallest allowed value, according to the system clock
speed.
0: SYSCLK < 25 MHz (Flash read strobe is one system clock).
1: SYSCLK > 25 MHz (Flash read strobe is two system clocks).
R/W
Bit6
SFR Definition 16.3. FLSCL: Flash Scale
R/W
Bit5
FLRT
R/W
Bit4
Reserved Reserved Reserved Reserved 00000011
Rev. 1.0
R/W
Bit3
R/W
Bit2
R/W
Bit1
SFR Address:
R/W
Bit0
0xB6
Reset Value