c8051f410 Silicon Laboratories, c8051f410 Datasheet - Page 66

• Manufacturer Part Number: c8051f410
• Description: 2.0 V, 32/16 Kb Flash, Smartclock, 12-bit Adc
• Manufacturer: Silicon Laboratories

C8051F410/1/2/3
5.4.1. Window Detector In Single-Ended Mode
Figure 5.7
ADC0LTH:ADC0LTL = 0x0200 (512d) and ADC0GTH:ADC0GTL = 0x0100 (256d). The input voltage can
range from ‘0’ to V
value. The repeat count is set to one. In the left example, an AD0WINT interrupt will be generated if the
ADC0 conversion word (ADC0H:ADC0L) is within the range defined by ADC0GTH:ADC0GTL and
ADC0LTH:ADC0LTL (if 0x0100 < ADC0H:ADC0L < 0x0200). In the right example, and AD0WINT interrupt
will be generated if the ADC0 conversion word is outside of the range defined by the ADC0GT and
ADC0LT registers (if ADC0H:ADC0L < 0x0100 or ADC0H:ADC0L > 0x0200). Figure 5.8 shows an exam-
ple using left-justified data with the same comparison values.
66
Figure 5.7. ADC Window Compare Example: Right-Justified Single-Ended Data
VREF x (4095/4096)
VREF x (4095/4096)
VREF x (512/4096)
VREF x (256/4096)
Figure 5.8. ADC Window Compare Example: Left-Justified Single-Ended Data
VREF x (512/4096)
VREF x (256/4096)
Input Voltage
(Px.x - GND)
Input Voltage
(Px.x - GND)
0
0
shows
ADC0H:ADC0L
ADC0H:ADC0L
REF
0x0FFF
0x01FF
0x00FF
0xFFF0
0x1FF0
0x0FF0
0x0201
0x0200
0x0101
0x0100
0x0000
0x2010
0x2000
0x1010
0x1000
0x0000
x (4095/4096) with respect to GND, and is represented by a 12-bit unsigned integer
two
example
ADC0GTH:ADC0GTL
ADC0LTH:ADC0LTL
ADC0GTH:ADC0GTL
ADC0LTH:ADC0LTL
not affected
not affected
AD0WINT
AD0WINT
not affected
not affected
AD0WINT
AD0WINT
AD0WINT=1
window
AD0WINT=1
Rev. 1.0
VREF x (512/4096)
VREF x (256/4096)
comparisons
VREF x (4095/4096)
VREF x (512/4096)
VREF x (256/4096)
VREF x (4095/
Input Voltage
(Px.x - GND)
Input Voltage
(Px.x - GND)
4096)
0
0
ADC0H:ADC0L
ADC0H:ADC0L
0x0FFF
0x0201
0x0200
0x01FF
0x0101
0x0100
0x00FF
0x0000
for
0xFFF0
0x1FF0
0x0FF0
0x2010
0x2000
0x1010
0x1000
0x0000
right-justified
ADC0GTH:ADC0GTL
ADC0LTH:ADC0LTL
ADC0GTH:ADC0GTL
ADC0LTH:ADC0LTL
not affected
AD0WINT
not affected
AD0WINT
AD0WINT=1
AD0WINT=1
data
AD0WINT=1
AD0WINT=1
with