km416rd8as Samsung Semiconductor, Inc., km416rd8as Datasheet - Page 19

• Manufacturer Part Number: km416rd8as
• Description: 128mbit Rdram 256k X 16 Bit X 2*16 Dependent Banks Direct Rdramtm For Consumer Package
• Manufacturer: Samsung Semiconductor, Inc.

KM416RD8AS
ROW-to-ROW Examples
Figure 10 shows examples of some of the ROW-to-ROW
packet spacings from Table 10. A complete sequence of acti-
vate and precharge commands is directed to a bank. The
RR8 and RR12 rules apply to this sequence. In addition to
satisfying the t
Figure 11 shows examples of the ACT-to-ACT (RR1, RR2)
and ACT-to-PRER (RR5, RR6) command spacings from
Table 10. In general, the commands in ROW packets may be
spaced an interval t
COL4
COL4
CTM/CFM
CTM/CFM
DQA7..0
DQA7..0
ROW2
DQB7..0
ROW2
DQB7..0
..COL0
..COL0
..ROW0
..ROW0
RAS
t
T
T
PACKET
0
0
ACT a0
ACT a0
T
T
1
1
and t
PACKET
T
T
2
2
T
T
3
3
RP
T
T
4
4
ACT b0
timing parameters, the separation
T
T
apart unless they are directed to
5
5
T
T
6
6
t
T
T
t
RAS
7
7
RC
T
T
8
8
T
T
9
9
T
T
10
10
T
T
11
11
T
T
12
12
ACT a0
T
T
Figure 10: Row Packet Example
Figure 11: Row Packet Example
13
13
T
T
14
14
T
T
15
15
T
T
16
16
T
T
17
17
T
T
18
18
T
T
t
19
19
Page 16
RR
Same Device
Same Device
Same Device
Same Device
Same Device
T
T
20
20
ACT c0
T
T
21
Different Device
Different Device
21
between ACT commands to the same bank must also satisfy
the t
When a bank is activated, it is necessary for adjacent banks
to remain precharged. As a result, the adjacent banks will
also satisfy parallel timing constraints; in the example, the
RR11 and RR3 rules are analogous to the RR12 and RR4
rules.
the same or adjacent banks or unless they are a similar
command type (both PRER or both ACT) directed to the
same device.
T
Same Device
Same Device
T
22
22
T
T
23
23
RC
T
T
PRER a1
24
24
T
T
timing parameter (RR4).
25
25
T
T
26
26
T
T
27
27
t
Adjacent Bank
Adjacent Bank
Adjacent Bank
T
T
PACKET
28
28
Same Bank
Same Bank
ACT a0
T
T
Non-adjacent Bank
Non-adjacent Bank
29
29
T
T
30
30
Any Bank
Any Bank
T
T
t
31
31
RP
T
T
PRER b0
32
32
ACT b0
T
T
33
33
T
T
34
34
T
T
RR11
RR12
35
35
Target
Direct RDRAM
RR7
RR3
RR4
Rev. 0.9 July 1999
T
T
36
36
T
T
37
37
RR1
RR2
RR5
RR6
T
T
38
38
T
T
39
39
t
T
T
PACKET
40
40
b0 = {Da,Ba+1,Rb}
b0 = {Da,Ba+1,Rb}
ACT a0
b0 = {Da,Ba,Rb}
b0 = {Da,Ba,Rb}
T
b0 = {Db,Bb,Rb}
b0 = {Db,Bb,Rb}
T
a0 = {Da,Ba,Ra}
a0 = {Da,Ba,Ra}
c0 = {Da,Bc,Rc}
c0 = {Da,Bc,Rc}
a1 = {Da,Ba+1}
41
41
T
T
42
42
T
T
43
43
T
T
44
44
PRER c0
T
T
45
45
T
T
46
46
T
T
47
47
™