km416rd8as Samsung Semiconductor, Inc., km416rd8as Datasheet - Page 33

• Manufacturer Part Number: km416rd8as
• Description: 128mbit Rdram 256k X 16 Bit X 2*16 Dependent Banks Direct Rdramtm For Consumer Package
• Manufacturer: Samsung Semiconductor, Inc.

KM416RD8AS
Control Register Summary
Table 16 summarizes the RDRAM control registers. Detail
is provided for each control register in Figure 27 through
Figure 43. Read-only bits which are shaded gray are unused
and return zero. Read-write bits which are shaded gray are
reserved and should always be written with zero. The RIMM
SA11..SA0
021
022
023
024
040
041
042
043
044
045
046
047
048
16
16
16
16
16
16
16
16
16
16
16
16
16
Register
INIT
TEST34
CNFGA
CNFGB
DEVID
REFB
REFR
CCA
CCB
NAPX
PDNXA
PDNX
TPARM
Field
SDEVID
PSX
SRP
NSR
PSR
LSR
TEN
TSQ
DIS
TEST34
REFBIT
DBL
MVER
PVER
BYT
DEVTYP
SPT
CORG
SVER
DEVID
REFB
REFR
CCA
ASYMA
CCB
ASYMB
NAPXA
NAPX
DQS
PDNXA
PDNX
TCAS
TCLS
TCDLY0
read-write/ read-only
read-write, 6 bits
read-write, 1 bit
read-write, 1 bit
read-write, 1 bit
read-write, 1 bit
read-write, 1 bit
read-write, 1 bit
read-write, 1 bit
read-write, 1 bit
read-write, 16 bits
read-only, 3 bit
read-only, 1 bit
read-only, 6 bit
read-only, 6 bit
read-only, 1 bit
read-only, 3 bit
read-only, 1 bit
read-only, 6 bit
read-only, 6 bit
read-write, 5 bits
read-write, 4 bits
read-write, 9 bits
read-write, 7 bits
read-write, 2 bits
read-write, 7 bits
read-write, 2 bits
read-write, 5 bits
read-write, 5 bits
read-write, 1 bits
read-write, 13 bits
read-write, 13 bits
read-write, 2 bits
read-write, 2 bits
read-write, 3 bits
Table 16: Control Register Summary
Description
Serial device ID. Device address for control register read/write.
Power select exit. PDN/NAP exit with device addr on DQA5..0.
SIO repeater. Used to initialize RDRAM.
NAP self-refresh. Enables self-refresh in NAP mode.
PDN self-refresh. Enables self-refresh in PDN mode.
Low power self-refresh. Enables low power self-refresh.
Temperature sensing enable.
Temperature sensing output.
RDRAM disable.
Test register. Do not read or write after SIO reset.
Refresh bank bits. Used for multi-bank refresh.
Double. Specifies doubled-bank architecture
Manufacturer version. Manufacturer identification number.
Protocol version. Specifies version of Direct protocol supported.
Byte. Specifies an 8-bit or 9-bit byte size.
Device type. Device can be RDRAM or some other device category.
Split-core. Each core half is an individual dependent core.
Core organization. Bank, row, column address field sizes.
Stepping version. Mask version number.
Device ID. Device address for memory read/write.
Refresh bank. Next bank to be refreshed by self-refresh.
Refresh row. Next row to be refreshed by REFA, self-refresh.
Current control A. Controls I
Asymmetry control. Controls asymmetry of V
Current control B. Controls I
Asymmetry control. Controls asymmetry of V
NAP exit. Specifies length of NAP exit phase A.
NAP exit. Specifies length of NAP exit phase A + phase B.
DQ select. Selects CMD framing for NAP/PDN exit.
PDN exit. Specifies length of PDN exit phase A.
PDN exit. Specifies length of PDN exit phase A + phase B.
t
t
t
Page 30
CAS-C
CLS-C
CDLY0-C
core parameter. Determines t
core parameter. Determines t
SPD Application Note describes additional read-only
configuration registers which are present on Direct RIMMs.
The state of the register fields are potentially affected by the
IO Reset operation or the SETR/CLRR operation. This is
indicated in the text accompanying each register diagram.
core parameter. Programmable delay for read data.
OL
OL
output current for DQB.
output current for DQA.
CAC
OFFP
and t
datasheet parameter.
OFFP
Target
Direct RDRAM
Rev. 0.9 July 1999
OL
OL
/V
/V
parameters.
OH
OH
swing for DQA.
swing for DQB.
™