km416rd8as Samsung Semiconductor, Inc., km416rd8as Datasheet - Page 26

• Manufacturer Part Number: km416rd8as
• Description: 128mbit Rdram 256k X 16 Bit X 2*16 Dependent Banks Direct Rdramtm For Consumer Package
• Manufacturer: Samsung Semiconductor, Inc.

KM416RD8AS
Write/Retire Examples - continued
The RD will prevent a retire of the first WR from automati-
cally happening. But the first dualoct D(a1) in the write
buffer will be overwritten by the second WR dualoct D(b1)
if the RD command is issued in the third COLC packet.
Figure 19 shows a possible result when a retire is held off for
a long time (an extended version of Figure 18-left). After a
WR command, a series of six RD commands are issued to
the same device (but to any combination of bank and column
addresses). In the meantime, the bank Ba to which the WR
command was originally directed is precharged, and a
different row Rc is activated. When the retire is automati-
cally performed, it is made to this new row, since the write
COL4
COL4
CTM/CFM
CTM/CFM
DQA7..0
DQA7..0
ROW2
DQB7..0
ROW2
DQB7..0
..COL0
..COL0
..ROW0
..ROW0
T
T
Transaction a: WR
Transaction c: WR
Transaction b: RD
Figure 19: Retire Held Off by Reads to Same Device, Write Buffer Retired to New Row
0
0
ACT a0
WR a1
T
T
Transaction a: WR
Transaction b: RD
Figure 18: Retire Held Off by Read (left) and Controller Forces WWR Gap (right)
1
1
T
T
The retire operation for a write can be
2
2
held off by a read to the same device
T
T
3
3
T
T
4
4
T
T
5
5
t
T
T
CWD
t
6
6
RTR
T
T
t
7
7
RCD
T
T
8
8
b1 = {Da,Bb,Cb1}
b4 = {Da,Bb,Cb4}
+ t
RD b1
a0 = {Da,Ba,Ra}
c0 = {Da,Ba,Rc}
T
T
9
9
WR a1
PACKET
T
T
10
10
b1= {Da,Bb,Cb1}
a1= {Da,Ba,Ca1}
D (a1)
T
T
11
11
T
T
retire (a1)
MSK (a1)
12
12
T
T
13
13
T
T
14
14
t
t
T
T
CAC
CWD
15
15
t
RAS
t
T
T
RTR
16
16
T
T
17
17
b2 = {Da,Bb,Cb2}
b5 = {Da,Bb,Cb5}
a1 = {Da,Ba,Ca1}
RD b1
T
T
18
18
T
T
19
19
Page 23
t
D (a1)
T
T
RC
20
20
Q (b1)
T
T
21
21
CTM/CFM
COL4
RD b2
DQA7..0
Therefore, it is required in this situation that the controller
issue a NOCOP command in the third COLC packet,
delaying the RD command by a time of t
tion is explicitly shown in Table 12 for the cases in which
t
ROW2
DQB7..0
buffer only contains the bank and column address, not the
row address. The controller can insure that this doesn’t
happen by never precharging a bank with an unretired write
buffer. Note that in a system with more than one RDRAM,
there will never be more than two RDRAMs with unretired
write buffers. This is because a WR command issued to one
device automatically retires the write buffers of all other
devices written a time t
T
T
CCDELAY
22
22
..COL0
..ROW0
T
T
t
23
23
CAC
T
PRER a2
24
T
25
RD b3
T
26
b6 = {Da,Bb,Cb6}
b3= {Da,Bb,Cb3}
is equal to t
T
27
a2 = {Da,Ba}
T
T
28
0
The controller must insert a NOCOP to retire (a1)
WR a1
Q (b1)
to make room for the data (b1) in the write buffer
T
T
Transaction a: WR
Transaction b: WR
Transaction c: RD
29
1
RD b4
T
T
30
2
T
T
t
3
31
RP
RTR
T
T
RTR
4
32
ACT c0
WR b1
Q (b2)
T
T
5
33
.
t
RD b5
T
T
CWD
before or earlier.
34
6
t
T
T
RTR
35
7
Target
Direct RDRAM
Rev. 0.9 July 1999
T
T
and must be used with caution
retire (a1)
MSK (a1)
36
8
The retire operation puts the
This sequence is hazardous
Q (b3)
T
T
9
37
write data in the new row
RD b6
T
T
10
38
b1= {Da,Bb,Cb1}
a1= {Da,Ba,Ca1}
c1= {Da,Bc,Cc1}
D (a1)
T
T
11
39
WARNING
T
T
PACKET
12
40
RD c1
Q (b4)
T
T
retire (a1)
13
MSK (a1)
41
T
T
14
42
D (b1)
T
T
15
43
. This situa-
T
T
44
16
Q (b5)
T
T
45
17
T
T
t
18
46
CAC
T
T
19
47
™
T
20