km416rd8as Samsung Semiconductor, Inc., km416rd8as Datasheet - Page 8

• Manufacturer Part Number: km416rd8as
• Description: 128mbit Rdram 256k X 16 Bit X 2*16 Dependent Banks Direct Rdramtm For Consumer Package
• Manufacturer: Samsung Semiconductor, Inc.

KM416RD8AS
General Description
Figure 2 is a block diagram of the 128 Mbit Direct RDRAM.
It consists of two major blocks: a “core” block built from
banks and sense amps similar to those found in other types
of DRAM, and a Direct Rambus interface block which
permits an external controller to access this core at up to
1.6GB/s.
Control Registers:
pins appear in the upper center of Figure 2. They are used to
write and read a block of control registers. These registers
supply the RDRAM configuration information to a
controller and they select the operating modes of the device.
The nine bit REFR value is used for tracking the last
refreshed row. Most importantly, the five bit DEVID speci-
fies the device address of the RDRAM on the Channel.
Clocking:
generate TCLK (Transmit Clock), the internal clock used to
transmit read data. The CFM and CFMN pins (Clock-From-
Master) generate RCLK (Receive Clock), the internal clock
signal used to receive write data and to receive the ROW and
COL pins.
DQA,DQB Pins:
(D) data across the Channel. They are multiplexed/de-multi-
plexed from/to two 64-bit data paths (running at one-eighth
the data frequency) inside the RDRAM.
Banks:
sixteen 0.5Mbyte banks, each organized as 512 rows, with
each row containing 64 dualocts, and each dualoct
containing 16 bytes. A dualoct is the smallest unit of data
that can be addressed.
Sense Amps:
amps. Each sense amp consists of 512 bytes of fast storage
(256 for DQA and 256 for DQB) and can hold one-half of
one row of one bank of the RDRAM. The sense amp may
hold any of the 512 half-rows of an associated bank.
However, each sense amp is shared between two adjacent
banks of the RDRAM (except for numbers 0, 15, 16, and
31). This introduces the restriction that adjacent banks may
not be simultaneously accessed.
RQ Pins:
tion. They are broken into two groups. RQ7..RQ5 are also
called ROW2..ROW0, and are used primarily for controlling
row accesses. RQ4..RQ0 are also called COL4..COL0, and
are used primarily for controlling column accesses.
ROW Pins:
manage the transfer of data between the banks and the sense
amps of the RDRAM. These pins are de-multiplexed into a
The 16Mbyte core of the RDRAM is divided into
These pins carry control and address informa-
The CTM and CTMN pins (Clock-To-Master)
The principle use of these three pins is to
The RDRAM contains two sets of 17 sense
These 16 pins carry read (Q) and write
The CMD, SCK, SIO0, and SIO1
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24-bit ROWA (row-activate) or ROWR (row-operation)
packet.
COL Pins:
manage the transfer of data between the DQA/DQB pins and
the sense amps of the RDRAM. These pins are de-multi-
plexed into a 23-bit COLC (column-operation) packet and
either a 17-bit COLM (mask) packet or a 17-bit COLX
(extended-operation) packet.
ACT Command:
ROWA packet causes one of the 512 rows of the selected
bank to be loaded to its associated sense amps (two 256 byte
sense amps for DQA and two for DQB).
PRER Command:
an ROWR packet causes the selected bank to release its two
associated sense amps, permitting a different row in that
bank to be activated, or permitting adjacent banks to be acti-
vated.
RD Command:
the 64 dualocts of one of the sense amps to be transmitted on
the DQA/DQB pins of the Channel.
WR Command:
dualoct received from the DQA/DQB data pins of the
Channel to be loaded into the write buffer. There is also
space in the write buffer for the BC bank address and C
column address information. The data in the write buffer is
automatically retired (written with optional bytemask) to one
of the 64 dualocts of one of the sense amps during a subse-
quent COP command. A retire can take place during a RD,
WR, or NOCOP to another device, or during a WR or
NOCOP to the same device. The write buffer will not retire
during a RD to the same device. The write buffer reduces the
delay needed for the internal DQA/DQB data path turn-
around.
PREC Precharge:
commands are similar to PREC, RD and WR, except that a
precharge operation is scheduled at the end of the data
transfer. These commands provide a second mechanism for
performing precharge.
PREX Precharge:
command with no byte masking (M=0), a COLX packet may
be used to specify an extended operation (XOP). The most
important XOP command is PREX. This command provides
a third mechanism for performing precharge.
The principle use of these five pins is to
The RD (read) command causes one of
The WR (write) command causes a
An ACT (activate) command from an
The NOP, RDA and WRA
After a RD command, or after a WR
A PRER (precharge) command from
Target
Direct RDRAM
Rev. 0.9 July 1999
™