km416rd8as Samsung Semiconductor, Inc., km416rd8as Datasheet - Page 24

• Manufacturer Part Number: km416rd8as
• Description: 128mbit Rdram 256k X 16 Bit X 2*16 Dependent Banks Direct Rdramtm For Consumer Package
• Manufacturer: Samsung Semiconductor, Inc.

KM416RD8AS
Write Transaction - Example
Figure 16 shows an example of a write transaction. It begins
by activating a bank with an ACT a0 command in an ROWA
packet. A time t
in a COLC packet (note that the t
the end of the COLC packet with the first retire command).
Note that the ACT command includes the device, bank, and
row address (abbreviated as a0) while the WR command
includes device, bank, and column address (abbreviated as
a1). A time t
dualoct D(a1) is issued. Note that the packets on the ROW
and COL pins use the end of the packet as a timing reference
point, while the packets on the DQA/DQB pins use the
beginning of the packet as a timing reference point.
A time t
second COLC packet is issued. It contains a WR a2
command. The a2 address has the same device and bank
address as the a1 address (and a0 address), but a different
column address. A time t
command a second write data dualoct D(a2) is issued.
A time t
packet MSK (a1) is issued, and at the same time a COLC
packet is issued causing the write buffer to automatically
retire. See Figure 17 for more detail on the write/retire
mechanism. If a COLM packet is not used, all data bytes are
unconditionally written. If the COLC packet which causes
COL4
CTM/CFM
DQA7..0
ROW2
DQB7..0
..COL0
..ROW0
CC
RTR
after the first COLC packet on the COL pins a
CWD
after each WR command an optional COLM
Transaction a: WR
T
RCD
Transaction b: xx
0
ACT a0
after the WR command the write data
T
1
-t
T
2
RTR
T
3
T
CWD
4
later a WR a1 command is issued
T
5
T
6
after the second WR
T
t
7
RCD
RCD
T
8
b0 = {Da,Ba,Rb}
a0 = {Da,Ba,Ra}
T
9
interval is measured to
WR a1
T
10
T
11
Figure 16: Write Transaction Example
T
12
T
13
WR a2
T
t
t
14
CC
RTR
t
T
CWD
15
t
RAS
T
16
T
retire (a1)
MSK (a1)
17
a1 = {Da,Ba,Ca1}
T
18
t
T
CWD
19
Page 21
t
D (a1)
T
RC
20
T
retire (a2)
MSK (a2)
21
t
RTR
the write buffer to retire is delayed, then the COLM packet
(if used) must also be delayed.
Next, a PRER a3 command is issued in an ROWR packet on
the ROW pins. This causes the bank to precharge so that a
different row may be activated in a subsequent transaction or
so that an adjacent bank may be activated. The a3 address
includes the same device and bank address as the a0, a1, and
a2 addresses. The PRER command must occur a time t
or more after the original ACT command (the activation
operation in any DRAM is destructive, and the contents of
the selected row must be restored from the two associated
sense amps of the bank during the t
A PRER a3 command is issued in an ROWR packet on the
ROW pins. The PRER command must occur a time t
more after the last COLC which causes an automatic retire.
Finally, an ACT b0 command is issued in an ROWR packet
on the ROW pins. The second ACT command must occur a
time t
or more after the PRER command. This ensures that the
bank and its associated sense amps are precharged. This
example assumes that the second transaction has the same
device and bank address as the first transaction, but a
different row address. Transaction b may not be started until
transaction a has finished. However, transactions to other
banks or other devices may be issued during transaction a.
T
22
T
23
D (a2)
T
24
RC
T
25
PRER a3
or more after the first ACT command and a time t
T
26
a2 = {Da,Ba,Ca2}
T
27
T
28
T
29
t
RTP
T
30
T
31
T
t
32
RP
T
33
ACT b0
T
34
T
35
Target
Direct RDRAM
Rev. 0.9 July 1999
T
36
a3 = {Da,Ba}
T
37
RAS
T
38
T
39
interval).
T
40
T
41
T
42
T
43
T
44
T
45
RTP
T
RAS
46
T
or
47
RP
™