km416rd8as Samsung Semiconductor, Inc., km416rd8as Datasheet - Page 48

• Manufacturer Part Number: km416rd8as
• Description: 128mbit Rdram 256k X 16 Bit X 2*16 Dependent Banks Direct Rdramtm For Consumer Package
• Manufacturer: Samsung Semiconductor, Inc.

KM416RD8AS
a. With V
b. Effective setup becomes t
if [PDNX•256•t
Symbol
t
t
t
t
t
t
t
t
t
t
v
v
t
t
t
t
t
t
t
t
t
t
t
t
t
t
CYCLE1
CH1
S1
H1
S2
H2
S3
H3
S4
H4
NPQ
READTOCC
CCSAMTOREAD
CE
CD
FRM
NLIMIT
REF
CCTRL
TEMP
TCEN
TCAL
TCQUIET
PAUSE
IL,CMOS
IH,CMOS
, t
CL1
IL,CMOS
SCYCLE
=0.5V
] < [PDNXA•64•t
CMOS
Parameter
SCK cycle time - Serial control register transactions
SCK cycle time - Power transitions
SCK high and low times
CMD setup time to SCK rising or falling edge
CMD hold time to SCK rising or falling edge
SIO0 setup time to SCK falling edge
SIO0 hold time to SCK falling edge
PDEV setup time on DQA5..0 to SCK rising edge.
PDEV hold time on DQA5..0 to SCK rising edge.
ROW2..0, COL4..0 setup time for quiet window
ROW2..0, COL4..0 hold time for quiet window
CMOS input low voltage - over/undershoot voltage duration is less
than or equal to 5ns
CMOS input high voltage - over/undershoot voltage duration is
less than or equal to 5ns
Quiet on ROW/COL bits during NAP/PDN entry
Offset between read data and CC packets (same device)
Offset between CC packet and read data (same device)
CTM/CFM stable before NAP/PDN exit
CTM/CFM stable after NAP/PDN entry
ROW packet to COL packet ATTN framing delay
Maximum time in NAP mode
Refresh interval
Current control interval
Temperature control interval
TCE command to TCAL command
TCAL command to quiet window
Quiet window (no read data)
RDRAM delay (no RSL operations allowed)
S4
-0.6V and V
’ =t
S4
+[PDNXA•64•t
SCYCLE
IH,CMOS
+t
=0.5V
PDNXB,MAX
SCYCLE
CMOS
Table 19: Timing Conditions
+t
PDNXB,MAX
+0.6V
]. See Figure 48.
c
a
b
]-[PDNX•256•t
Page 45
SCYCLE
34 t
V
]
CMOS
+ 0.6
1000
Min
4.25
- 0.7
100
150
140
5.5
10
40
35
12
CYCLE
-1
1
1
0
5
4
8
2
7
2
/2
V
V
CMOS
100ms
CMOS
200.0
Max
10.0
100
0.6
0.7
32
2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
/2 -
+
Target
Direct RDRAM
Rev. 0.9 July 1999
ms/t
t
t
t
t
t
t
t
t
t
t
t
CYCLE
CYCLE
CYCLE
CYCLE
CYCLE
CYCLE
CYCLE
CYCLE
CYCLE
CYCLE
CYCLE
Unit
ms
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
CYCLE
V
V
s
s
Figure 48,
Figure(s)
Figure 56
Figure 56
Figure 56
Figure 56
Figure 56
Figure 56
Figure 56
Figure 57
Figure 48
Figure 48
Figure 47
Figure 51
Figure 51
Figure 48
Figure 47
Figure 46
Figure 45
Figure 50
Figure 51
Figure 52
Figure 52
Figure 52
Figure 52
page 28
™