km416rd8as Samsung Semiconductor, Inc., km416rd8as Datasheet - Page 43

• Manufacturer Part Number: km416rd8as
• Description: 128mbit Rdram 256k X 16 Bit X 2*16 Dependent Banks Direct Rdramtm For Consumer Package
• Manufacturer: Samsung Semiconductor, Inc.

KM416RD8AS
PDEV5..0 address packet and exits NAP or PDN when the
wake-up sequence is presented on the CMD wire. The ROW
and COL pins must be quiet at a time t
cated falling SCK edge (timed with the PDNX or NAPX
register fields). After that, ROW and COL packets may be
directed to the RDRAM which is now in ATTN or STBY
state.
On the right side of Figure 48, an RDRAM exits PDN state
at the end of cycle T
or NAP state for an interval of t
PDN state at the end of cycle T
COL4
COL4
CTM/CFM
CTM/CFM
DQA7..0
Power
DQA7..0
Power
ROW2
DQB7..0
ROW2
DQB7..0
State
State
..COL0
..COL0
..ROW0
..ROW0
a
The (eventual) NAP/PDN exit will be to the same ATTN/STBY state the RDRAM was in prior to NAP/PDN entry
T
T
0
0
T
T
1
1
ROP a0
COP a0
XOP a0
(NAPR)
RLXR
RLXC
RLXX
T
T
3
2
2
. This RDRAM may not re-enter PDN
ATTN/STBY
T
T
3
ATTN
3
T
T
4
4
T
T
5
5
restricted
restricted
quiet
quiet
t
T
T
NPQ
6
6
t
13
T
AS
T
PU0
7
7
. This RDRAM may not re-
t
T
T
t
ASN
8
Figure 46: STBY Entry (left) and STBY Exit (right)
8
CD
. The RDRAM enters
Figure 47: NAP Entry (left) and PDN Entry (right)
T
T
a
9
9
ROP a1
COP a1
XOP a1
S4
T
T
10
10
/t
STBY
T
T
11
11
H4
T
T
12
12
around the indi-
T
T
13
13
NAP
T
T
14
14
T
T
15
15
T
T
16
16
COL4
COL4
CTM/CFM
CTM/CFM
DQA7..0
DQB7..0
Power
DQA7..0
DQB7..0
Power
T
ROW2
T
ROW2
State
State
17
17
..COL0
..COL0
..ROW0
..ROW0
T
T
18
18
T
T
19
19
Page 40
T
T
20
20
T
T
21
21
Figure 49 shows the constraints for entering and exiting
NAP and PDN states. On the left side, an RDRAM exits
NAP state at the end of cycle T
enter NAP or PDN state for an interval of t
RDRAM enters NAP state at the end of cycle T
RDRAM may not re-exit NAP state for an interval of t
The equations for these two parameters depend upon a
number of factors, and are shown at the bottom of the figure.
NAPX is the value in the NAPX field in the NAPX register.
exit PDN state for an interval of t
these two parameters depend upon a number of factors, and
are shown at the bottom of the figure. PDNX is the value in
the PDNX field in the PDNX register.
T
T
22
22
T
T
T
T
23
0
23
0
T
T
1
1
ROP a0
ROP a0
(PDNR)
COP a0
XOP a0
T
T
2
2
t
SA
ATTN/STBY
STBY
T
T
3
3
T
T
4
4
T
T
restricted
restricted
5
5
quiet
quiet
t
T
T
NPQ
6
TFRM•t
6
T
T
7
7
COP a1
XOP a1
t
T
T
t
ASP
CD
8
8
COP a1
XOP a1
T
T
a
9
9
COP a1
XOP a1
ROP a1
COP a1
XOP a1
T
T
10
CYCLE
10
COP a1
XOP a1
T
T
11
ATTN
11
COP a0
XOP a0
T
T
12
12
Target
Direct RDRAM
Rev. 0.9 July 1999
3
T
T
PDN
. This RDRAM may not re-
13
13
PU1
T
T
14
14
T
T
15
15
. The equations for
T
T
16
16
T
T
a0 = {d0,b0,r0,c0}
a1 = {d1,b1,r1,c1}
No ROW or COL packets
directed to device d0 may
overlap the restricted
interval. No broadcast ROW
packets may overlap the quiet
interval.
ROW or COL packets to a
device other than d0 may
overlap the restricted
interval.
ROW or COL packets
directed to device d0 after the
restricted interval will be
ignored.
17
17
ROP = non-broadcast ROWA
or ROWR/ATTN
a0 = {d0,b0,r0}
a1 = {d1,b1,c1}
No COL packets may be
placed in the three
indicated positions; i.e. at
A COL packet to device d0
(or any other device) is okay
at
or later.
A COL packet to another
device (d1!= d0) is okay at
or earlier.
T
T
NU0
(TFRM - {1,2,3})•t
(TFRM)•t
(TFRM - 4)•t
18
18
T
T
19
19
. The
T
T
13
20
20
CYCLE
T
T
. This
21
21
CYCLE
T
T
22
22
T
T
NU1
CYCLE
23
23
™
.
.