am79c974 Advanced Micro Devices, am79c974 Datasheet - Page 145

• Manufacturer Part Number: am79c974
• Description: Pcnettm-scsi Combination Ethernet And Scsi Controller For Pci Systems
• Manufacturer: Advanced Micro Devices

Target Abort
Figure 13 shows a target abort sequence. The target as-
serts DEVSEL for one clock. It then deasserts DEVSEL
and asserts STOP on clock 4. A target can use the target
abort sequence to indicate that it cannot service the data
transfer and that it does not want the transaction to be
retried. Additionally, the Am79C974 controller cannot
make any assumption about the success of the previous
data transfers in the current transaction. The
Am79C974 controller terminates the current transfer
with the deassertion of FRAME on clock 5 and one clock
cycle later with the deassertion of IRDY. It finally re-
leases the bus on clock 6.
DEVSEL
FRAME
TRDY
STOP
IRDY
C/BE
REQ
GNT
PAR
CLK
AD
1
DEVSEL is sampled by the Am79C974 controller.
ADDR
0111
Figure 13. Target Abort
2
A M E N D M E N T
DATA
Am79C974
PAR
3
0000
Since data integrity is not guaranteed, the Am79C974
controller cannot recover from a target abort event. For
Ethernet, the Am79C974 controller will reset all CSR
and BCR locations to their H_RESET values. Any
on-going network activity will be stopped immediately.
The PCI configuration registers will not be cleared. For
SCSI, when target aborts, INTA will not be asserted, but
the ABORT bit (bit 2 of the DMA status register at offset
54h), is set. For either Ethernet or SCSI a target abort
causes RTABORT (bit 12) of the status register in the
appropriate PCI configuration space to be set.
PAR
4
5
6
18681A/1-17
AMD
11