am79c974 Advanced Micro Devices, am79c974 Datasheet - Page 83

• Manufacturer Part Number: am79c974
• Description: Pcnettm-scsi Combination Ethernet And Scsi Controller For Pci Systems
• Manufacturer: Advanced Micro Devices

continue until the Current Transfer Count Register dec-
rements to zero.
Non-DMA commands do not modify the Current Trans-
fer Count Register and are unaffected by the value in the
Current Transfer Count Register. For non-DMA com-
mands, the number of bytes transmitted depends solely
on the operation in progress.
When non-DMA commands are used, the host com-
puter must use programmed I/O to transfer the data be-
tween the SCSI FIFO and the host memory.
Command Stacking
The microprocessor may stack commands in the Com-
mand Register ((B)+0Ch) since it functions as a two-
byte deep FIFO. Non-DMA commands may not be
stacked, and commands which transfer data in oppos-
ing directions should not be stacked together; other-
wise, the results are unpredictable.
If DMA commands are queued together, the Start
Transfer Count must be written before the associated
command is loaded into the Command Register. Since
Notes:
* These commands do not generate interrupt.
** An interrupt is generated when SCSI bus reset interrupt
Initiator Commands
Information Transfer
Initiator Command Complete Steps
Message Accepted
Transfer Pad Bytes
Set ATN*
Reset ATN*
Idle State Commands
Select without ATN Steps
Select with ATN Steps
Select with ATN and Stop Steps
Enable Selection/Reselection*
Disable Selection/Reselection
Select with ATN3 Steps
General Commands
No Operation*
Clear FIFO*
Reset Device*
Reset SCSI Bus**
reporting is not disabled (see Control Register1/DISR
bit6).
Table 7. Summary of Commands
Command
Mode
Non-
DMA
1A
1B
10
11
12
41
42
43
44
45
46
00
01
02
03
–
(Hex.)
Code
P R E L I M I N A R Y
Mode
DMA
C1
C2
C3
C4
C6
90
91
98
80
–
–
–
–
–
–
–
Am79C974
multiple interrupts can occur when commands are
stacked, it is recommended that the ENF bit in Control
Register Two (Bit 6) be set in order to latch the SCSI
phase bits in the SCSI Status Register ((B)+10h) at the
completion of a command. This allows the host to deter-
mine the phase of the interrupting command without
having to consider phase changes that occurred after
the stacked command began execution.
Note: Command stacking should only be used during
SCSI Data In or Data Out transfers.
Invalid Commands
When an illegal command is written to the Am79C974,
the Invalid Command Bit (Bit 6, Register (B)+14h) will be
set to ‘1’, and an interrupt will be generated to the host.
When this happens, the interrupt must be serviced be-
fore another command may be written to the Command
Register.
An Invalid command is defined as a command written to
the Am79C974 that is either not supported, not allowed
in the specified mode, or a command that has an unsup-
ported command mode.
The following conditions will also cause an Invalid Com-
mand interrupt to occur:
Command Window
The window at the point where the Disable Selection/
Reselection command (45h/C5h) has been loaded into
the Command Register ((B)+0Ch), and before bus-initi-
ated Selection begins, has been eliminated. This pre-
vents a false Successful Operation Interrupt from being
generated when the Selection sequence continues to
completion after the Disable command has been
loaded.
Initiator Commands
Initiator commands are executed by the device when it
is in the Initiator mode. If the device is not in the Initiator
mode and an Initiator command is received the device
will ignore the command, generate an Invalid Command
interrupt and clear the Command Register.
Should the Target disconnect from the SCSI bus by
deasserting the BSY signal line while the Am79C974
(Initiator) is waiting for the Target to assert REQ, a Dis-
connected Interrupt will be issued 1.5 to 3.5 clock cycles
following BSY going false.
Upon receipt of the last byte during Message In phase,
ACK will remain asserted to prevent the Target from is-
suing any additional bytes, while the Initiator decides to
An Initiator Information Transfer, Transfer Pad, or
Command Complete is issued when ACK is still
asserted.
A Selection command is issued with the DMA bit
enabled, if the Selection command was previously
issued with the DMA enabled.
AMD
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