am79c974 Advanced Micro Devices, am79c974 Datasheet - Page 44

• Manufacturer Part Number: am79c974
• Description: Pcnettm-scsi Combination Ethernet And Scsi Controller For Pci Systems
• Manufacturer: Advanced Micro Devices

rently has ownership of this ring descriptor and its
associated buffer. Only the owner is permitted to relin-
quish ownership or to write to any field in the descriptor
entry. A device that is not the current owner of a descrip-
tor entry cannot assume ownership or change any field
in the entry. A device may, however, read from a de-
scriptor that it does not currently own. Software should
always read descriptor entries in sequential order.
When software finds that the current descriptor is owned
by the Am79C974 controller, then the software must not
read “ahead” to the next descriptor. The software should
wait at the unOWNed descriptor until ownership has
been granted to the software (when LAPPEN = 1
(CSR3, bit 5), then this rule is modified. See the LAP-
PEN description). Strict adherence to these rules in-
sures that “Deadly Embrace” conditions are avoided.
Descriptor Ring Access Mechanism
At initialization, the Am79C974 controller reads the
44
AMD
RES
RLEN
TLEN
CSR2
IADR[23:16]
Initialization
24-Bit Base Address
RES
RES
LADRF[15:0]
LADRF[31:16]
LADRF[47:32]
LADRF[63:48]
RDRA[15:0]
TDRA[15:0]
PADR[15:0]
PADR[31:16]
PADR[47:32]
Initialization Block
Figure 17. 16-Bit Data Structures: Initialization Block and Descriptor Rings
Block
MODE
Pointer to
RDRA[23:16]
TDRA[23:16]
IADR[15:0]
CSR1
P R E L I M I N A R Y
Buffers
Buffers
Xmt
Am79C974
Rcv
1st desc.
start
base address of both the transmit and receive descriptor
rings into CSRs for use by the Am79C974 controller dur-
ing subsequent operations.
As the final step in the self-initialization process, the
base address of each ring is loaded into each of the cur-
rent descriptor address registers and the address of the
next descriptor entry in the transmit and receive rings is
computed and loaded into each of the next descriptor
address registers.
When SSIZE32 = 0, software data structures are 16 bits
wide. The following diagram, Figure 17, illustrates the
relationship between the Initialization Base Address,
the Initialization Block, the Receive and Transmit De-
scriptor Ring Base Addresses, the Receive and Trans-
mit Descriptors and the Receive and Transmit Data
Buffers, for the case of SSIZE32 = 0.
RMD0
1st desc.
start
TMD0
RX DESCRIPTOR RINGS
RX DESCRIPTOR RINGS
Buffer
Buffer
Data
Data
1
1
RMD1 RMD2
N
TMD1 TMD2
Rcv Descriptor
Xmt Descriptor
M
Ring
Ring
Buffer
Buffer
N
Data
Data
2
2
M
RMD3
TMD3
N
M
2nd desc.
start
2nd desc.
start
RMD0
N
TMD0
M
•
Buffer
Buffer
Data
Data
•
•
M
N
•
•
•
18681A-21