am79c974 Advanced Micro Devices, am79c974 Datasheet - Page 53

• Manufacturer Part Number: am79c974
• Description: Pcnettm-scsi Combination Ethernet And Scsi Controller For Pci Systems
• Manufacturer: Advanced Micro Devices

The oscillator requires an external 0.01% timing refer-
ence. The accuracy requirements, if an external crystal
is used are tighter because allowance for the on-board
parasitics must be made to deliver a final accuracy of
0.01%.
Transmission is enabled by the controller. As long as the
ITXEN request remains active, the serial output of the
controller will be Manchester encoded and appear at
DO . When the internal request is dropped by the con-
troller, the differential transmit outputs go to one of two
idle states, dependent on TSEL in the Mode Register
(CSR15, bit 9):
Input Signal Conditioning
Transient noise pulses at the input data stream are re-
jected by the Noise Rejection Filter. Pulse width rejec-
tion is proportional to transmit data rate, (which is fixed
at 10 MHz for Ethernet but could be different for proprie-
tary networks). DC inputs more negative than minus
100 mV are also surpressed.
The Carrier Detection circuitry detects the presence of
an incoming data frame by discerning and rejecting
noise from expected Manchester data, and controls the
stop and start of the phase-lock loop during clock acqui-
sition. Clock acquisition requires a valid Manchester bit
pattern of 1010b to lock onto the incoming message.
When input amplitude and pulse width conditions are
met at DI , the internal enable signal from the MENDEC
to controller (IRXCRS) is asserted and a clock acquisi-
tion cycle is initiated.
DI
TSEL LOW:
TSEL HIGH: In this idle state, DO+ is positive with
*Internal signal
The idle state of DO yields “ZERO”
differential to operate transformer-
coupled loads.
respect to DO– (logical HIGH).
Receiver
Reject
Noise
Data
Filter
Figure 19. Receiver Block Diagram
P R E L I M I N A R Y
Am79C974
Receiver Path
The principal functions of the Receiver are to signal the
Am79C974 controller that there is information on the re-
ceive pair, and separate the incoming Manchester en-
coded data stream into clock and NRZ data.
The Receiver section (see Receiver Block Diagram)
consists of two parallel paths. The receive data path is a
ZERO threshold, wide bandwidth line receiver. The car-
rier path is an offset threshold bandpass detecting line
receiver. Both receivers share common bias networks
to allow operation over a wide input common
mode range.
Clock Acquisition
When there is no activity at DI (receiver is idle), the re-
ceive oscillator is phase locked to internal transmit
clock. The first negative clock transition (bit cell center of
first valid Manchester “0”) after IRXCRS is asserted in-
terrupts the receive oscillator. The oscillator is then re-
started at the second Manchester “0” (bit time 4) and is
phase locked to it. As a result, the MENDEC acquires
the clock from the incoming Manchester bit pattern in
4 bit times with a 1010b Manchester bit pattern.
The internal serial receive data clock, ISRDCLK and the
internal received data, IRXDAT, are enabled 1/4 bit time
after clock acquisition in bit cell 5. IRXDAT is at a HIGH
state when the receiver is idle (no ISRDCLK). IRXDAT
however, is undefined when clock is acquired and may
remain HIGH or change to LOW state whenever
ISRDCLK is enabled. At 1/4 bit time through bit cell 5,
Manchester
Decoder
Carrier
Detect
Circuit
IRXDAT*
ISRDCLK*
IRXCRS*
AMD
18681A-23
53