am79c974 Advanced Micro Devices, am79c974 Datasheet - Page 84

• Manufacturer Part Number: am79c974
• Description: Pcnettm-scsi Combination Ethernet And Scsi Controller For Pci Systems
• Manufacturer: Advanced Micro Devices

accept/reject the message. If non-DMA commands are
used, the last byte signals the SCSI FIFO is empty. If
DMA commands are used, the Current Transfer Count
signals the last byte.
A Reset SCSI Bus command (03h/83h) will force the
Am79C974 to abort the current operation and discon-
nect from the bus. If the DISR bit is reset (Bit 6, Control
Register One (B)+20h)), the host processor will be inter-
rupted with a SCSI Reset Interrupt before the
Am79C974 proceeds to Disconnect.
If parity checking is enabled in the Initiator mode during
the Data-in phase and an error is detected, ATN will be
asserted for the erroneous byte before deasserting
ACK.
Information Transfer Command
(Command Code 10h/90h)
The Information Transfer command is used to transfer
information bytes over the SCSI bus. This command
may be issued during any SCSI Information Transfer
phase. Synchronous data transmission requires use of
the DMA mode.
The device will continue to transfer information until it is
terminated by any one of the following conditions:
During Synchronous Data transfers the Target may
send up to the maximum synchronous offset number of
REQ pulses to the Initiator. If it is the Synchronous Data-
In phase then the Target sends the data and the REQ
pulses. These bytes are stored by the Initiator in the
FIFO as they are received.
The Information Transfer Command, when issued dur-
ing the following SCSI phases and terminated in Syn-
chronous Data phases, is handled as described below:
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The Target changes the SCSI bus phase before
the expected number of bytes are transferred. The
Am79C974 clears the Command Register
(CMDREG), and generates a Service Request
interrupt when the Target asserts REQ.
Transfer has successfully completed. If the phase
is Message Out, the Am79C974 deasserts ATN
before asserting ACK for the last byte of the mes-
sage. When the Target asserts REQ, a Service
Request interrupt is generated.
In the Message In phase when the device receives
the last byte. The Am79C974 keeps the ACK sig-
nal asserted and generates a Successful Opera-
tion interrupt.
Message In/Status Phase – When a phase change
to Synchronous Data-In or Synchronous Data-Out
is detected by the device, the Command Register
AMD
P R E L I M I N A R Y
Am79C974
Initiator Command Complete Steps
(Command Code 11h/91h)
The Initiator Command Complete Steps command is
normally issued when the SCSI bus is in the Status In
phase. One Status byte followed by one Message byte
is transferred if this command completes normally. After
receiving the message byte the device will keep the
ACK signal asserted to allow the Initiator to examine the
message and assert the ATN signal if it is unacceptable.
The command terminates early if the Target does not
is cleared and the DMA interface is disabled to
prevent any transfer of data (phase) bytes.
If the phase change is to Synchronous Data-In and
bad parity is detected on the data bytes coming in,
it is not reported since the Status Register will re-
port the status of the command just completed.
The parity error flag and the ATN signal will be
asserted when the next Information Transfer com-
mand begins execution.
Message Out/Command Phase – When a phase
change to Synchronous Data-In or Synchronous
Data-Out is detected by the device, the Command
Register is cleared and the DMA interface is dis-
abled to prevent any transfer of data (phase)
bytes.
If the phase change is to Synchronous Data-In and
bad parity is detected on the data bytes coming in,
it is not reported since the Status Register will re-
port the status of the command just completed.
The parity error flag and the ATN signal will be as-
serted when the next Information Transfer com-
mand begins execution.
The SCSI FIFO Register will be latched and will
remain in that condition until the next command
begins execution. The value in the SCSI FIFO
Register indicates the number of non-data bytes in
the SCSI FIFO when the phase changed to Syn-
chronous Data-In. These bytes are cleared from
the FIFO, and only incoming data bytes are re-
tained.
In the Synchronous Data-Out phase, the threshold
counter is incremented as REQ pulses are re-
ceived. The transfer is completed when the FIFO is
empty and the Current Transfer Count Register is
‘0’. The threshold counter will not be ‘0’.
In the Synchronous Data-In phase, the Current
Transfer Count Register is decremented as bytes
are read from the SCSI FIFO rather than when the
bytes are being written to the SCSI FIFO. The
transfer is completed when Current Transfer Count
Register is ‘0’. However, the SCSI FIFO may not
be empty.