am79c974 Advanced Micro Devices, am79c974 Datasheet - Page 61

• Manufacturer Part Number: am79c974
• Description: Pcnettm-scsi Combination Ethernet And Scsi Controller For Pci Systems
• Manufacturer: Advanced Micro Devices

Accesses of non word quantities to any I/O resource are
not allowed while in WIO mode, with the exception of a
read to APROM locations. (A write access may cause
unexpected reprogramming of the Ethernet controller
control registers; a read access will yield undefined
values.)
The Vendor Specific Word (VSW) is not implemented by
the Ethernet controller. This particular I/O address is re-
served for customer use and will not be used by future
AMD Ethernet controller products.
DWIO I/O Resource Map
When the Ethernet controller I/O space is mapped as
Double Word I/O, then all of the resources that are allot-
ted to the Ethernet controller occur on DWORD bounda-
ries that are offset from the Ethernet controller I/O base
address as shown in the table below:
When Ethernet I/O space is Double Word mapped, all
I/O resources fall on DWORD boundaries. APROM re-
sources are DWORD quantities in DWIO mode. RDP,
RAP and BDP contain only two bytes of valid data; the
other two bytes of these resources are reserved for fu-
ture use. (Note that CSR88 is an exception to this rule.)
The reserved bits must be written as ZEROs, and when
read, are considered undefined.
Accesses to non-doubleword address boundaries are
not allowed while in DWIO mode. (A write access may
cause unexpected reprogramming of the Ethernet con-
troller control registers; a read access will yield unde-
fined values.)
Accesses of less than 4 bytes to any I/O resource are
not allowed while in DWIO mode. (A write access may
cause unexpected reprogramming of the Ethernet con-
troller control registers; a read access will yield unde-
fined values.)
If an EEPROM is not used to program the value of
DWIO, then a DWORD write access to the RDP offset of
10h will automatically program DWIO mode.
Note that in all cases when I/O resource width is defined
as 32 bits, the upper 16 bits of the I/O resource is
Offset
1Ch
10h
14h
18h
Ch
0h
4h
8h
No. of
Bytes
4
4
4
4
4
4
4
4
RAP (shared by RDP and BDP)
Reset Register
Register
APROM
APROM
APROM
APROM
RDP
BDP
P R E L I M I N A R Y
Am79C974
reserved and written as ZEROS and read as undefined,
except for the APROM locations and CSR88.
DWIO mode is exited by asserting the RST pin or by
forcing a re-read of the EEPROM when the EEPROM
will program a ZERO into the DWIO bit location of
BCR10. Assertion of S_RESET or setting the STOP bit
of CSR0 will have no effect on the DWIO mode setting.
I/O Space Comments
The following statements apply to both WIO and DWIO
mapping:
The RAP is shared by the RDP and the BDP.
The Ethernet controller does not respond to any ad-
dresses outside of the offset range 0h–17h when DWIO
= 0 or 0h–1Fh when DWIO = 1. I/O offsets 18h through
1Fh are not used by the Ethernet controller when pro-
grammed for DWIO = 0 mode; locations 1Ah through
1Fh are reserved for future AMD use and therefore
should not be implemented by the user if upward com-
patibility to future AMD devices is desired.
Note that APROM accesses do not directly access the
EEPROM, but are redirected to a set of shadow regis-
ters on board the Ethernet controller that contain a copy
of the EEPROM contents that was obtained during the
automatic EEPROM read operation that follows the
H_RESET operation.
Am79C974’s Ethernet Controller I/O Base Address
The Ethernet PCI Configuration Space Base Address
register defines what I/O base address the Ethernet
controller uses. This register is typically programmed by
the PCI configuration utility after system power-up. The
PCI configuration utility must also set the IOEN bit in the
COMMAND register to enable I/O accesses to the
Ethernet controller.
The contents of the Ethernet I/O Base Address Regis-
ters (BCR16 and BCR17) are ignored.
I/O Register Access
All I/O resources are accessed with similar I/O bus
cycles.
I/O accesses to the Ethernet controller begin with a valid
FRAME signal, the C/BE[3:0] lines signaling an I/O read
or I/O write operation and an address on the AD[31:00]
lines that falls within the I/O space of the Ethernet con-
troller. The Ethernet I/O space will be determined by the
Base Address Register in the PCI Configuration Space.
The Ethernet controller will respond to an access to its
I/O space by asserting the DEVSEL signal and eventu-
ally, by asserting the TRDY signal.
Typical I/O access times are 6 or 7 clock cycles.
AMD
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