am79c974 Advanced Micro Devices, am79c974 Datasheet - Page 48

• Manufacturer Part Number: am79c974
• Description: Pcnettm-scsi Combination Ethernet And Scsi Controller For Pci Systems
• Manufacturer: Advanced Micro Devices

Receive Descriptor Table Entry (RDTE)
If the Am79C974 controller does not own both the cur-
rent and the next Receive Descriptor Table Entry then
the Am79C974 controller will continue to poll according
to the polling sequence described above. If the receive
descriptor ring length is 1, then there is no next descrip-
tor to be polled.
If a poll operation has revealed that the current and the
next RDTE belong to the Am79C974 controller then ad-
ditional poll accesses are not necessary. Future poll op-
erations will not include RDTE accesses as long as the
Am79C974 controller retains ownership of the current
and the next RDTE.
When receive activity is present on the channel, the
Am79C974 controller waits for the complete address of
the message to arrive. It then decides whether to accept
or reject the frame based on all active addressing
schemes. If the frame is accepted the Am79C974 con-
troller checks the current receive buffer status register
CRST (CSR41) to determine the ownership of the cur-
rent buffer.
If ownership is lacking, then the Am79C974 controller
will immediately perform a (last ditch) poll of the current
RDTE. If ownership is still denied, then the Am79C974
controller has no buffer in which to store the incoming
message. The Missed Frame Count register (CSR112)
will be incremented and the MISS bit will be set in CSR0
and an interrupt will be generated if IENA=1 (CSR0) and
MISSM=0 (CSR3). Another poll of the current RDTE will
not occur until the frame has finished.
If the Am79C974 controller sees that the last poll (either
a normal poll, or the last-ditch effort described in the
above paragraph) of the current RDTE shows valid own-
ership, then it proceeds to a poll of the next RDTE. Fol-
lowing this poll, and regardless of the outcome of this
poll, transfers of receive data from the FIFO may begin.
Regardless of ownership of the second receive descrip-
tor, the Am79C974 controller will continue to perform re-
ceive data DMA transfers to the first buffer. If the frame
length exceeds the length of the first buffer, and the
Am79C974 controller does not own the second buffer,
ownership of the current descriptor will be passed back
to the system by writing a ZERO to the OWN bit of
RMD1 and status will be written indicating buffer
(BUFF=1) and possibly overflow (OFLO=1) errors.
If the frame length exceeds the length of the first (cur-
rent) buffer, and the Am79C974 controller does own the
second (next) buffer, ownership will be passed back to
the system by writing a ZERO to the OWN bit of RMD1
when the first buffer is full. Receive data transfers to the
second buffer may occur before the Am79C974 control-
ler proceeds to look ahead to the ownership of the third
buffer. Such action will depend upon the state of the
FIFO when the status has been updated on the first de-
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AMD
P R E L I M I N A R Y
Am79C974
scriptor. In any case, lookahead will be performed to the
third buffer and the information gathered will be stored in
the chip, regardless of the state of the ownership bit. As
in the transmit flow, lookahead operations are per-
formed only once.
This activity continues until the Am79C974 controller
recognizes the completion of the frame (the last byte of
this receive message has been removed from the
FIFO). The Am79C974 controller will subsequently up-
date the current RDTE status with the end of frame
(ENP) indication set, write the message byte count
(MCNT) of the complete frame into RMD2 and overwrite
the “current” entries in the CSRs with the “next” entries.
Media Access Control
The Media Access Control engine incorporates the es-
sential protocol requirements for operation of a compli-
ant Ethernet/802.3 node, and provides the interface
between the FIFO sub-system and the Manchester En-
coder/Decoder (MENDEC).
The MAC engine is fully compliant to Section 4 of ISO/
IEC 8802-3 (ANSI/IEEE Standard 1990 Second edition)
and ANSI/IEEE 802.3 (1985).
The MAC engine provides programmable enhanced
features designed to minimize host supervision, bus
utilization, and pre- or post- message processing.
These include the ability to disable retries after a colli-
sion, dynamic FCS generation on a frame-by-frame ba-
sis, and automatic pad field insertion and deletion to
enforce minimum frame size attributes, automatic
retransmission without reloading the FIFO, automatic
deletion of collision fragments, and reduces bus
bandwidth use.
The two primary attributes of the MAC engine are:
Transmit and Receive Message Data
Encapsulation
The MAC engine provides minimum frame size enforce-
ment for transmit and receive frames. When
APAD_XMT = 1 (CSR, bit 11), transmit messages will
be padded with sufficient bytes (containing 00h) to en-
sure that the receiving station will observe an informa-
tion field (destination address, source address,
length/type, data and FCS) of 64-bytes. When
Transmit and receive message data encapsulation.
— Framing (frame boundary delimitation, frame
— Addressing (source and destination address
— Error detection (physical medium transmission
Media access management.
— Medium allocation (collision avoidance).
— Contention resolution (collision handling).
synchronization).
handling).
errors).