am79c974 Advanced Micro Devices, am79c974 Datasheet - Page 76

• Manufacturer Part Number: am79c974
• Description: Pcnettm-scsi Combination Ethernet And Scsi Controller For Pci Systems
• Manufacturer: Advanced Micro Devices

wider PCI bus. All boundary conditions are handled
through hardware by the DMA Engine.
The DMA engine is also designed for block type (4
KByte page) transfers to support scatter-gather opera-
tions. Implementation of this feature is described further
in the DMA Scatter-Gather Mechanism section.
DMA FIFO
Data transfers from the SCSI FIFO to the DMA FIFO
take place each time the threshold of two bytes is
reached on the SCSI side. The transfer is initiated by the
SCSI block when the internal DREQ is asserted, and
continues with the DACK handshaking which typically
takes place in DMA accesses. Data is accumulated in
the DMA FIFO until a threshold of 16 DWORD (64 bytes)
is reached. Data is then burst across the PCI bus to
memory. Residue data which is less than the threshold
in each FIFO is sent in non-contiguous bursts. For mem-
ory read operations, data is sent in burst mode to the
DMA FIFO and continues through to the SCSI FIFO and
onto the SCSI bus.
DMA BLAST Command
This command is used to retrieve the contents of the
DMA FIFO when the Target disconnects during a DMA
Write operation. This could happen for example if a
SCSI disk drive detected the end of a sector and de-
cided to give up the bus while it was looking for the next
sector. The Target Disconnect can leave some bytes of
data in the DMA FIFO and some in the SCSI FIFO, while
some bytes have yet to be transferred from the periph-
eral device. When this happens, the controller will assert
INTA to interrupt the processor, the SCSI state machine
will continue to empty its contents into the DMA FIFO,
but the DMA FIFO will not necessarily dump its contents
into memory (unless the 64-byte DMA threshold hap-
pens to have been exceeded at this time).
The BLAST command causes the contents of the DMA
FIFO to be emptied into memory. There are some re-
strictions on when this command should be used.
(This is a test for a special case that can occur when a
Target Disconnect leaves only 1 byte left to be trans-
ferred from the SCSI peripheral. In this case, if the origi-
nal transfer count was even, an odd number of bytes will
be left in the SCSI FIFO. Since the SCSI engine trans-
fers data to the DMA FIFO two bytes at a time, the last
76
First, the command should be used only to recover
from an interrupted DMA write operation—not a
read operation.
Second, the command must not be issued until the
SCSI FIFO has finished dumping its contents into
the DMA FIFO.
Third, the command should never be issued when
the DMA FIFO has already been emptied. This is
indicated by the state of the DONE bit in the DMA
STATUS register at ((B)+54h).
AMD
P R E L I M I N A R Y
Am79C974
transfer consists of one byte of valid data and one byte
of garbage. The DMA engine treats this final invalid byte
as valid data and writes it to memory. When it does this,
it decrements its Working Byte Counter to zero and sets
the DONE bit, even though 1 byte still needs to be re-
trieved from the peripheral device.)
The following procedure outlines the use of the BLAST
command after an interrupt has occurred. Note that the
order of steps 2–4 is not critical. The order can be
changed to tune the performance. Also note that each
register is read only once in this procedure even though
several tests may be made on data from one register.
1. Verify that INT (bit 7 of the SCSI status register at
2. Read the SCSI current FIFO count (bits 4:0 of the
3. If bit 4 of the SCSI status register (CTZ) is set,
4. Verify that DIR (bit 7 of DMA command register at
5. Test the error bits in the DMA status register and
6. Test the DMA DONE bit in the DMA STATUS
7. Wait until the BLAST complete (BCMPLT) in the
8. Write ‘00’ to the DMA command register to issue
The above procedure insures that the data that has
been transferred from the SCSI peripheral does not get
lost in the DMA FIFO when a Target Disconnect occurs.
However, it does not complete the original transfer. The
software must now read the SCSI Current Transfer
Count register (CTCREG) to find out how many bytes
have yet to be transferred from the SCSI peripheral de-
vice and must start a new transfer operation to get the
rest of the data. (CTCREG consists of three bytes lo-
cated at ((B)+00h, (B)+04h, and (B)+38h.)
Funneling Logic
Figure 26 shows the internal DMA logic interface with
the SCSI block. The DMA FIFO interfaces to the Funnel
((B)+10h) is set to indicate that a SCSI interrupt is
pending.
Current FIFO/Internal State register at ((B)+1Ch).
If this value is not zero, wait for the SCSI FIFO to
empty its contents into the DMA FIFO.
stop here. The transfer is complete, and it is not
necessary to execute the BLAST command.
((B)+40h) is set to one to indicate that the direction
of transfer is from SCSI to memory.
the SCSI status register (STATREG at (B)+10h) to
verify that the contents of the DMA and SCSI
FIFOs are not invalid.
register. If DONE is not set, write ‘01’ to the DMA
command register to issue the BLAST command.
This will move the remaining data from the DMA
FIFO into memory.
DMA STATUS register is set to indicate the com-
pletion of the BLAST operation.
the IDLE command to the DMA engine. (Note
that the IDLE command does not generate an
interrupt.)