am79c974 Advanced Micro Devices, am79c974 Datasheet - Page 24

• Manufacturer Part Number: am79c974
• Description: Pcnettm-scsi Combination Ethernet And Scsi Controller For Pci Systems
• Manufacturer: Advanced Micro Devices

SCSI Controller Pins
SCSI Bus Interface Signals
SCSI Bus Pins
SD [7:0]
SCSI Data
Input/Output, Active Low, Open Drain/Active
Negation, Schmitt Trigger
These pins are defined as bi-directional SCSI data bus.
SDP
SCSI Data Parity
Input/Output, Active Low, Open Drain/Active
Negation, Schmitt Trigger
This pin is defined as bi-directional SCSI data parity.
MSG
Message
Input, Active Low, Schmitt Trigger
It is a Schmitt trigger input in the initiator mode.
C/D
Command/Data
Input, Schmitt Trigger
It is a Schmitt trigger input in the initiator mode.
I/O
Input/Output
Input, Schmitt Trigger
It is a Schmitt trigger input in the initiator mode.
ATN
Attention
Output, Active Low, Open Drain
This signal is a 48 mA output in the initiator mode. This
signal will be asserted when the device detects a parity
error; also, it can be asserted via certain commands.
BSY
Busy
Input/Output, Active Low, Schmitt Trigger,
Open Drain
As a SCSI input signal it has a Schmitt trigger and as an
output signal it has a 48 mA drive.
SEL
Select
Input/Output, Active Low, Schmitt Trigger,
Open Drain
As a SCSI input signal it has a Schmitt trigger and as an
output signal it has a 48 mA drive.
24
AMD
P R E L I M I N A R Y
Am79C974
SCSI^RST
Reset
Input/Output
Open Drain
As a SCSI input signal it has a Schmitt trigger and as an
output signal it has a 48 mA drive.
REQ
Request
Input, Active Low, Schmitt Trigger
This is a SCSI input signal with a Schmitt trigger in the
initiator mode.
ACK
Acknowledge
Output
This is a SCSI output signal with a 48 mA drive in the
initiator mode.
SCSI CLK
SCSI Clock
Input
The SCSI clock signal is used to generate all internal de-
vice timings. The maximum frequency of this input is
40 MHz and a minimum of 10 MHz is required to main-
tain the SCSI bus timings.
Note:
A 40 MHz clock must be supplied at this input to achieve
10 Mbyte/s Synchronous Fast SCSI transfers.
PWDN
Power Down Indicator
Input, Active High
This signal, when asserted, sets the PWDN status bit in
the DMA status register and sends an interrupt to
the host.
Test Interface
BUSY
NAND Tree Out
Output, Active Low
This signal is logically equivalent to the SCSI bus signal
BSY. It is duplicated so that external logic can be
connected to monitor SCSI bus activity.
The results of the NAND tree testing can be observed on
the BUSY pin where RST is asserted; otherwise, BUSY
will reflect the state of the SCSI Bus Signal line BSY
(pin 64).
,
Active Low, Open Drain/Active Negation
,
Active Low, Schmitt Trigger,