am79c974 Advanced Micro Devices, am79c974 Datasheet - Page 49

• Manufacturer Part Number: am79c974
• Description: Pcnettm-scsi Combination Ethernet And Scsi Controller For Pci Systems
• Manufacturer: Advanced Micro Devices

ASTRP_RCV = 1 (CSR4, bit 10), the receiver will
automatically strip pad bytes from the received mes-
sage by observing the value in the length field, and strip-
ping excess bytes if this value is below the minimum
data size (46 bytes). Both features can be independ-
ently over-ridden to allow illegally short (less than 64
bytes of frame data) messages to be transmitted and/or
received. The use of this feature reduces bus utilization
because the pad bytes are not transferred into or out of
main memory.
Framing (Frame Boundary Delimitation, Frame
Synchronization)
The MAC engine will autonomously handle the con-
struction of the transmit frame. Once the Transmit FIFO
has been filled to the predetermined threshold (set by
XMTSP in CSR80), and providing access to the channel
is currently permitted, the MAC engine will commence
the 7 byte preamble sequence (10101010b, where first
bit transmitted is a 1). The MAC engine will subse-
quently append the Start Frame Delimiter (SFD) byte
(10101011b) followed by the serialized data from the
Transmit FIFO. Once the data has been completed, the
MAC engine will append the FCS (most significant bit
first) which was computed on the entire data portion of
the frame. The data portion of the frame consists of des-
tination address, source address, length/type, and
frame data.
The user is responsible for the correct ordering and con-
tent in each of the fields in the frame.
The receive section of the MAC engine will detect an in-
coming preamble sequence and lock to the encoded
clock. The internal MENDEC will decode the serial bit
stream and present this to the MAC engine. The MAC
will discard the first 8-bits of information before search-
ing for the SFD sequence. Once the SFD is detected, all
subsequent bits are treated as part of the frame. The
MAC engine will inspect the length field to ensure mini-
mum frame size, strip unnecessary pad characters (if
enabled), and pass the remaining bytes through the Re-
ceive FIFO to the host. If pad stripping is performed, the
MAC engine will also strip the received FCS bytes, al-
though the normal FCS computation and checking will
occur. Note that apart from pad stripping, the frame will
be passed unmodified to the host. If the length field has
a value of 46 or greater, the MAC engine will not attempt
to validate the length against the number of bytes con-
tained in the message.
If the frame terminates or suffers a collision before
64-bytes of information (after SFD) have been received,
the MAC engine will automatically delete the frame from
the Receive FIFO, without host intervention. The
Am79C974 controller has the ability to accept runt pack-
ets for diagnostics purposes and proprietary networks.
P R E L I M I N A R Y
Am79C974
Addressing (Source and Destination Address
Handling)
The first 6-bytes of information after SFD will be inter-
preted as the destination address field. The MAC engine
provides facilities for physical, logical (multicast) and
broadcast address reception.
Error Detection (Physical Medium Transmission
Errors)
The MAC engine provides several facilities which report
and recover from errors on the medium. In addition, the
network is protected from gross errors due to inability of
the host to keep pace with the MAC engine activity.
On completion of transmission, the following transmit
status is available in the appropriate TMD and CSR
areas:
In addition to the reporting of network errors, the MAC
engine will also attempt to prevent the creation of any
network error due to the inability of the host to service
the MAC engine. During transmission, if the host fails to
keep the Transmit FIFO filled sufficiently, causing an un-
derflow, the MAC engine will guarantee the message is
either sent as a runt packet (which will be deleted by the
receiving station) or has an invalid FCS (which will also
cause the receiver to reject the message).
The exact number of transmission retry attempts
(ONE, MORE, RTRY or TRC).
Whether the MAC engine had to Defer (DEF) due
to channel activity.
Excessive deferral (EXDEF), indicating that the
transmitter has experienced Excessive Deferral on
this transmit frame, where Excessive Deferral is
defined in ISO 8802-3 (IEEE/ANSI 802.3).
Loss of Carrier (LCAR), indicating that there was
an interruption in the ability of the MAC engine to
monitor its own transmission. Repeated
LCAR errors indicate a potentially faulty trans-
ceiver or network connection.
Late Collision (LCOL) indicates that the transmis-
sion suffered a collision after the slot time. This is
indicative of a badly configured network. Late colli-
sions should not occur in a normal operating net-
work.
Collision Error (CERR) indicates that the trans-
ceiver did not respond with an SQE Test message
within the predetermined time after a transmission
completed. This may be due to a failed transceiver,
disconnected or faulty transceiver drop cable, or
the fact the transceiver does not support this fea-
ture (or it is disabled).
AMD
49