am79c974 Advanced Micro Devices, am79c974 Datasheet - Page 64

• Manufacturer Part Number: am79c974
• Description: Pcnettm-scsi Combination Ethernet And Scsi Controller For Pci Systems
• Manufacturer: Advanced Micro Devices

Hardware Access
PCnet-SCSI Controller Master Accesses
The Am79C974 controller has a bus interface compat-
ible with PCI specification revision 2.0.
Complete descriptions of the signals involved in bus
master transactions for each mode may be found in the
pin description section of this document. Timing dia-
grams for master accesses may be found in the block
description section for the Bus Interface Unit. This sec-
tion simply lists the types of master accesses that will be
performed by the Am79C974 controller with respect to
Note that all Am79C974 controller master read opera-
tions will always activate all byte enables. Therefore, no
one-, two- or three-byte read operations are indicated in
the table.
In the instance where a transmit buffer pointer address
begins on a non-DWORD boundary, the pointer will be
truncated to the next DWORD boundary address that
lies below the given pointer address and the first read
access from the transmit buffer will be indicated on the
byte enable signals as a four-byte read from this ad-
dress. Any data from byte lanes that lie outside of the
boundary indicated by the buffer pointer will be dis-
carded inside of the Am79C974 controller. Similarly, if
the end of a transmit buffer occurs on a non-DWORD
boundary, then all byte lanes will be indicated as active
by the byte enable signals, and any data from byte lanes
that lie outside of the boundary indicated by the buffer
pointer will be discarded inside of the Am79C974
controller.
64
* Cases marked with an asterisk represent extreme boundary conditions that are the result of programming one- and two-byte
Access
4-byte read
4-byte write
3-byte write
3-byte write
2-byte write
2-byte write
2-byte write
1-byte write
1-byte write
1-byte write
1-byte write
buffer sizes, and therefore will not be seen under normal circumstances.
AMD
Mode
Read
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Table 3. Bus Master Accesses
P R E L I M I N A R Y
Am79C974
BE[3:0]
1001*
1101*
1011*
0000
0000
1000
0001
1100
0011
1110
0111
data size and address information.
The Am79C974 controller will support master accesses
only to 32-bit peripherals. The Am79C974 controller
does not support master accesses to 8-bit or 16-bit
memory. The Am79C974 controller is not compatible
with 8-bit systems, since there is no mode that supports
Am79C974 controller accesses to 8-bit peripherals.
Table 3 describes all possible bus master accesses that
the Am79C974 controller will perform. The right most
column lists all operations that may execute the given
access:
Slave Access to I/O Resources
The Am79C974 device is always a 32-bit peripheral on
the system bus. However, the width of individual soft-
ware resources on board the Am79C974 controller may
be either 16-bits or 32-bits. The Am79C974 controller
I/O resource widths are determined by the setting of the
DWIO bit as indicated in the following table:
DWIO Setting Resource Width
DWIO = 0
DWIO = 1
Operation
descriptor read
or initialization block read
or transmit data buffer read
descriptor write
or receive data buffer write
receive data buffer write
receive data buffer write
receive data buffer write
receive data buffer write
receive data buffer write
receive data buffer write
receive data buffer write
receive data buffer write
descriptor write
or receive data buffer write
Controller I/O
Am79C974
16-bit
32-bit
Example Application
Existing PCnet-ISA
driver that assumes
16-bit I/O mapping
and 16-bit resource
widths
New drivers written
specifically for the
Am79C974 controller