am79c974 Advanced Micro Devices, am79c974 Datasheet - Page 80

• Manufacturer Part Number: am79c974
• Description: Pcnettm-scsi Combination Ethernet And Scsi Controller For Pci Systems
• Manufacturer: Advanced Micro Devices

When WAC (bits 11:0) again reaches the next 4K byte
boundary, the next MDL entry is read into the WAC. The
operation continues in this way until WMAC register
reaches the last MDL entry (Page Frame Address #n in
this example).
4. The WAC register points to the beginning of the last
DMA Scatter-Gather Operation
(Non-4k aligned elements MDL not set)
There is another way to implement a scatter-gather op-
eration which does not force the data elements to be
aligned on 4k boundaries. It assumes a “traditional”
scatter-gather list of the following format:
Element 0
Element 1
Element n
This second implementation is described as follows:
1. Set the SCSI Start Transfer Count Register
2. Program the DMA Starting Transfer Count Regis-
3. Program the DMA Starting Physical Address Reg-
4. Start the SCSI operation by issuing a SCSI Infor-
5. Start the DMA Engine with DMA Transfer Interrupt
6. When the Scatter-Gather element’s Byte Count
7. Reprogram the next Scatter-Gather element’s Byte
80
((B)+00h, (B)+04h, (B)+38h) to the Byte count of
the first Scatter-Gather element.
ter ((B)+44h) to the Byte Count of the first Scatter-
Gather element.
ister ((B)+48h) to the Physical Address of the first
Scatter-Gather element.
mation Transfer command.
Enable (Bit 6, (B)+40h).
is exhausted, the DMA engine will generate an
interrupt.
Count into the SCSI Start Transfer Count Register
and the DMA Starting Transfer Count Register.
AMD
WAC
31
Page Frame Address #n
Physical Address Byte Count
Physical Address Byte Count
...
Physical Address Byte Count
From the MDL
12
P R E L I M I N A R Y
WBC = 0
0
Am79C974
0
8. Reprogram the DMA Starting Physical Address
9. Repeat steps 4–8 until the Scatter-Gather list is
Interrupts
Interrupts may come from two sources: the DMA engine
or the SCSI block. Upon receipt of an interrupt (INTA as-
serted), the DMA Status register should be serviced first
to identify the interrupt source(s). DMA engine related
interrupts are cleared when the related flags are read in
the DMA Status register. However, SCSI block inter-
rupts will be cleared only when the SCSI Status, Internal
State, and Interrupt Status Registers are read.
Interrupts are caused by:
An interrupt from the SCSI block will automatically set
bit 4 (SCSIINT) in the DMA Status register (Address
(B)+54h). The SCSI block will generate an interrupt un-
der the following conditions:
page and the DMA operation continues until the
byte count is exhausted in the Working Byte
Counter (WBC) register. When WBC=0, the chip
stops incrementing the WAC register. This is
shown below.
Register ((B)+48h) to the Physical Address of the
next Scatter-Gather element.
completed.
Successful completion of a DMA transfer request.
(Bit 6 in the DMA Command Register ((B+40h)
must be set to enable this interrupt)
An address error occurred on the PCI bus during a
DMA transfer (Bit 6 in the DMA Command Regis-
ter ((B)+40h) must be set to enable this interrupt)
The PWDN pin is first asserted
After completion of each page transfer during MDL
operations. (Bit 5 in the DMA Command Register
((B)+40h) must be set to enable this interrupt)
SCSI Reset occurred
4K Page #n
Data
18681A/1-34