SAA7385GP Philips Semiconductors, SAA7385GP Datasheet - Page 20

• Manufacturer Part Number: SAA7385GP
• Description: Error correction and host interface IC for CD-ROM SEQUOIA
• Manufacturer: Philips Semiconductors

Philips Semiconductors
Table 7 Command execution times
All times indicated reflect two clock cycles per memory access for all accesses other than P and Q corrections. P and Q
corrections reflect seven clock cycles per memory access. Execution times will be extended due to refresh timing, other
buffer traffic, and configuration of nibble-wide memory.
8.3.1
Two registers are used to control the operation of the interrupt logic. The register INTRMSK allows each interrupt to be
enabled or disabled. INTRMSK and INTRFLG are cleared on reset to initially disable and clear all interrupts; the output
latch controlling the INT line is set on a reset; this must be cleared by writing 0x00 to INTRFLG. To enable an interrupt,
the bit that corresponds to the interrupt in INTRFLG must be set. The INTRFLG register shows the status of the
interrupts. If any bit is HIGH then an interrupt has occurred since the last time the bit was cleared. Writing a zero to any
bit location in INTRFLG will clear the corresponding interrupt. If a masked interrupt occurs, the microcontroller can still
detect the occurrence because the event is still posted in INTRFLG.
Table 8 Interrupt mask register: 0xF0FB
Each bit in register 0xF0FB corresponds to the interrupt at the same bit location in register 0xF0FC. To enable an
interrupt, the bit in this register must be set HIGH.
Table 9 Interrupt flag register: 0xF0FC
If any bit is set in this register (Table 9) then an interrupt may be sent to the microcontroller. Table 10 shows when the
interrupts are asserted; assuming the corresponding mask bit is set.
1996 Jun 19
CALCULATE_SYNDROMES (not Mode 2, Form 1)
CALCULATE_SYNDROMES (Mode 2, Form 1)
CRC_RECALCULATE (not Mode 2, Form 1)
CRC_RECALCULATE (Mode 2, Form 1)
COPY_RESULTS (not Mode 2, Form 1)
COPY_RESULTS (Mode 2, Form 1)
CORRECT_P_SYNDROMES
(maximum addition per correction)
CORRECT_Q_SYNDROMES
(maximum addition per correction)
TEST_ECC_RAM_READ
TEST_ECC_RAM_WRITE
MNEMONIC
MNEMONIC
INTRMSK
Error correction and host interface IC for
CD-ROM (SEQUOIA)
INTRFLG
I
NTERRUPT REGISTER DEFINITIONS
R/W
R/W
R/W
R/W
MASK7
7
COMMAND
7
FETXINT
MASK6
6
6
FERXINT ECC_COR FE_HDR
MASK5
5
5
20
MASK4
4
4
DATA BYTE
DATA BYTE
CYCLES
MASK3
5604
5600
4136
4120
1148
1156
1466
1184
1184
157
888
167
3
3
FE2352
MASK2
2
at 33 MHz
2
TIME ( s)
186.8
186.7
137.9
137.3
38.3
38.5
48.9
29.6
39.5
39.5
5.2
5.6
Preliminary specification
STR_LST FRM_STR
MASK1
1
1
SAA7385
ACCESSES
MEMORY
2658
2654
2068
2060
574
578
592
592
MASK0
0
2
0
2
0
0