SAA7385GP Philips Semiconductors, SAA7385GP Datasheet - Page 3

• Manufacturer Part Number: SAA7385GP
• Description: Error correction and host interface IC for CD-ROM SEQUOIA
• Manufacturer: Philips Semiconductors

Philips Semiconductors
1
1.1
1.2
1.3
1.4
1996 Jun 19
Single chip digital solution for an 8
controller chip
10 Mbytes/s NCR53CF94 equivalent SCSI controller
included
High-speed 80C32 microcontroller with 256
scratch-pad SRAM included
High performance CD-ROM interface logic
128 pin QFP package.
Separate clock input to allow operation up to the
maximum 10 Mbytes/s
Fast synchronous SCSI-2 compatible
24-bit transfer counter for single transfers up to
16 Mbytes
High-speed 16-bit DMA interface to the buffer manager
DRAM
On-chip 48 mA SCSI drivers
Software compatible with members of the 53C90 family
Allows for SCAM support.
33.87 MHz full system speed operation
Three timers/event counters
Programmable full duplex serial channel
Eight general purpose microcontroller I/O pins
External program ROM.
Full 8
Block decoder
Sector sequencer
CRC checking of Mode 1 and Mode 2, Form 1 sectors
212 ms watch-dog timer
Sub-code interface with synchronization
C-flag interface for absolute time stamp.
Error correction and host interface IC for
CD-ROM (SEQUOIA)
FEATURES
General
53CF94 SCSI controller
80C32 high-speed microcontroller
Front-end interface logic
speed hardware operation
speed CD-ROM
8
3
1.5
1.6
1.7
2
The SAA7385 is a high integration ASIC that incorporates
all of the digital electronics necessary to connect a CD
decoder to a SCSI host. An 80C32 microcontroller and a
53CF94 SCSI controller are embedded in the ASIC.
The following functions are supported:
Ten level arbitration logic
Utilizes low cost 70 ns DRAMs
Page mode DRAM access for high-speed error
correction and SCSI data transfer
Data organization by 3 kbyte frames
256 kbyte or 1 Mbyte DRAM supported.
Third-level correction provides superior performance in
unfavourable conditions
Full hardware error correction to reduce microcontroller
overhead
Corrections are automatically written to the DRAM
frame buffer.
All control registers mapped into 80C32 special function
memory space
Dedicated S2B interface UART
Input clock synthesizer
Red book audio pass through.
Input clock doubler
Block decoder
CRC checking of Mode 1 and Mode 2, Form 1 sectors
Red book audio pass through to SCSI
Buffer manager
Third-level error correction
Sub-code and Q-channel support
Dedicated S2B interface UART
Embedded 80C32 microcontroller
Embedded 53CF94 SCSI controller.
GENERAL DESCRIPTION
Buffer controller
Hardware third-level error correction
Additional product support
Preliminary specification
SAA7385