SAA7385GP Philips Semiconductors, SAA7385GP Datasheet - Page 27

• Manufacturer Part Number: SAA7385GP
• Description: Error correction and host interface IC for CD-ROM SEQUOIA
• Manufacturer: Philips Semiconductors

Philips Semiconductors
9.1
This section describes the registers used for the S2B UART control.
Table 28 S2B UART transmit, receive and status buffer: 0xF0A1, F0A2 and F0A3
Note
1. WTS2B is for the transmit data byte from the S2B UART and RDS2B is for the receive data byte from the S2B UART.
Table 29 S2BSTAT field description
Table 30 Baud rate generator control: 0xF0C0; note 1
Note
1. Register 0xF0C0 controls the S2B UART baud rate and selective inversion of the sub-code information. Control over
1996 Jun 19
WTS2B
RDS2B
S2BSTAT
RXDRDY
OVRRUN
PE
TXDRDY
CPR
SPR
MNEMONIC
MNEMONIC
Error correction and host interface IC for
CD-ROM (SEQUOIA)
BRGSEL
the parity and the clock doubler is also included together with the ability to invert the sub-code and Q-channel
information.
FIELD
S2B UART registers
(1)
A logic 1 indicates that the receive data is valid.
A logic 1 indicates that the data in the receive buffer was not read before it was over written by the next
byte.
A logic 1 indicates that a parity error was detected in the receive data byte; this is usually caused by the
wrong baud rate.
A logic 1 indicates that the transmit data buffer is empty and ready for another byte.
S2B handshake bit which may be interpreted as ‘clear to send’; this is generated automatically by the
UART. It is asserted whenever the UART receiver is ready for a byte and negated as soon as the stop
bit is shifted in. It is again asserted as soon as the received byte is read by the 80C32.
S2B handshake bit which may be interpreted as ‘request to send’; this is received from the CD-ROM
engine UART transmitter and will generate an interrupt to the 80C32 if the TXRDY bit is set and the
interrupt is not masked.
R/W
R/W
R/W
W
R
R
C_34_16
DATA7
DATA7
7
7
DATA6
DATA6
LOCK
6
6
EVENPAR INVSUBC
DATA5
DATA5
SPR
5
5
27
DESCRIPTION
DATA4
DATA4
CPR
4
DATA BYTE
DATA BYTE
4
TXDRDY
DATA3
DATA3
INVQ
3
3
DATA2
DATA2
PE
2
2
Preliminary specification
OVRRUN RXDRDY
ICESEL1
DATA1
DATA1
1
1
SAA7385
ICESEL0
DATA0
DATA0
0
0