SAA7385GP Philips Semiconductors, SAA7385GP Datasheet - Page 24

• Manufacturer Part Number: SAA7385GP
• Description: Error correction and host interface IC for CD-ROM SEQUOIA
• Manufacturer: Philips Semiconductors

Philips Semiconductors
9
This chapter describes the various SAA7385 control signals; front panel and basic engine signals, jumper settings and
use of the general purpose signals.
Table 16 Start clock doubler: 0xF091
A write of any value to this address will engage the clock doubler. The state of the doubler may be obtained by reading
C_34_16 in BRGSEL (see Table 30). If this bit is set then the clock doubler is engaged. On power-on, the clock doubler
is disabled. Once the clock doubler is engaged, it can only be reset by one of the reset sources; a power-on reset, a SCSI
reset or a reset from the watch-dog timer. The clock doubler must not be engaged when a 33.8688 MHz clock is
connected to OSCIN (pin 117).
Table 17 Frequency synthesizer test register: 0xF0D8; note 1
Note
1. Register 0xF0D8 is used for IC-level testing and to power down the frequency synthesizer. Only bit USE_IN should
Table 18 FSTEST field description
Table 19 Disconnected pulse-width modulator control: 0xF0B3; note 1
Note
1. Register 0xF0B3 is disconnected.
1996 Jun 19
FS_LOCK
FVCOD
CPSEL
USE_IN
MNEMONIC
MNEMONIC
MNEMONIC
Error correction and host interface IC for
CD-ROM (SEQUOIA)
WTPWM
CLKSEL
FSTEST
be asserted in normal operation.
FIELD
FRONT PANEL AND MISCELLANEOUS CONTROL SIGNALS
LOGIC
R/W
R/W
R/W
R/W
R/W
W
0
1
0
1
0
1
0
1
normal operation
3-state LED and switch LQDATA to FS_LOCK
normal operation
test mode for FVCOD from the synthesizer
normal operation
test mode for CPSEL from the synthesizer
use internal synthesizer
power down the synthesizer and operate off a 33.87 MHz input clock
7
7
7
6
6
6
USE_IN
5
5
5
24
CPSEL
DESCRIPTION
4
4
4
DATA BYTE
DATA BYTE
DATA BYTE
FVCOD
3
3
3
FS_LOCK
2
2
2
Preliminary specification
1
1
1
SAA7385
0
0
0