ADC08D1000DEV NSC [National Semiconductor], ADC08D1000DEV Datasheet - Page 24

• Manufacturer Part Number: ADC08D1000DEV
• Description: High Performance, Low Power, Dual 8-Bit, 1 GSPS A/D Converter
• Manufacturer: NSC [National Semiconductor]

www.national.com
1.0 Functional Description
The ADC08D1000 is a versatile A/D Converter with an inno-
vative architecture permitting very high speed operation. The
controls available ease the application of the device to circuit
solutions. Optimum performance requires adherence to the
provisions discussed here and in the Applications Information
Section.
While it is generally poor practice to allow an active pin to float,
pins 4, 14 and 127 of the ADC08D1000 are designed to be
left floating without jeopardy. In all discussions throughout this
data sheet, whenever a function is called by allowing a control
pin to float, connecting that pin to a potential of one half the
V
float.
1.1 OVERVIEW
The ADC08D1000 uses a calibrated folding and interpolating
architecture that achieves 7.5 effective bits. The use of folding
amplifiers greatly reduces the number of comparators and
power consumption. Interpolation reduces the number of
front-end amplifiers required, minimizing the load on the input
signal and further reducing power requirements. In addition
to other things, on-chip calibration reduces the INL bow often
seen with folding architectures. The result is an extremely
fast, high performance, low power converter.
The analog input signal that is within the converter's input
voltage range is digitized to eight bits at speeds of 200 MSPS
to 1.3 GSPS, typical. Differential input voltages below nega-
tive full-scale will cause the output word to consist of all
zeroes. Differential input voltages above positive full-scale
will cause the output word to consist of all ones. Either of
these conditions at either the "I" or "Q" input will cause the OR
(Out of Range) output to be activated. This single OR output
indicates when the output code from one or both of the chan-
nels is below negative full scale or above positive full scale.
Each of the two converters has a 1:2 demultiplexer that feeds
two LVDS output buses. The data on these buses provide an
output word rate on each bus at half the ADC sampling rate
and must be interleaved by the user to provide output words
at the full conversion rate.
The output levels may be selected to be normal or reduced.
Using reduced levels saves power but could result in erro-
neous data capture of some or all of the bits, especially at
higher sample rates and in marginally designed systems.
1.1.1 Self-Calibration
A self-calibration is performed upon power-up and can also
be invoked by the user upon command. Calibration trims the
100Ω analog input differential termination resistor and mini-
mizes full-scale error, offset error, DNL and INL, resulting in
maximizing SNR, THD, SINAD (SNDR) and ENOB. Internal
bias currents are also set with the calibration process. All of
this is true whether the calibration is performed upon power
up or is performed upon command. Running the self calibra-
tion is an important part of this chip's functionality and is
required in order to obtain adequate performance. In addition
to the requirement to be run at power-up, self calibration must
be re-run whenever the sense of the FSR pin is changed. For
best performance, we recommend that self calibration be run
20 seconds or more after application of power and whenever
the operating temperature changes significantly, according to
the system design performance specifications. See 2.4.2.2
On-Command Calibration for more information. Calibration
can not be initiated or run while the device is in the power-
down mode. See 1.1.7 Power Down for information on the
interaction between Power Down and Calibration.
A
supply voltage will have the same effect as allowing it to
24
During the calibration process, the input termination resistor
is trimmed to a value that is equal to R
resistor is located between pin 32 and ground. R
3300 Ω ±0.1%. With this value, the input termination resistor
is trimmed to be 100 Ω. Because R
proper current for the Track and Hold amplifier, for the pream-
plifiers and for the comparators, other values of R
not be used.
In normal operation, calibration is performed just after appli-
cation of power and whenever a valid calibration command is
given, which is holding the CAL pin low for at least t
cycles, then hold it high for at least another t
as defined in the Converter Electrical Characteristics. The
time taken by the calibration procedure is specified as t
Converter Electrical Characteristics. Holding the CAL pin high
upon power up will prevent the calibration process from run-
ning until the CAL pin experiences the above-mentioned
t
CalDly (pin 127) is used to select one of two delay times after
the application of power to the start of calibration. This cali-
bration delay time is depedent on the setting of the CalDly pin
and is specified as t
teristics. These delay values allow the power supply to come
up and stabilize before calibration takes place. If the PD pin
is high upon power-up, the calibration delay counter will be
disabled until the PD pin is brought low. Therefore, holding
the PD pin high during power up will further delay the start of
the power-up calibration cycle. The best setting of the CalDly
pin depends upon the power-on settling time of the power
supply.
Calibration Operation Notes:
•
•
•
1.1.2 Acquiring the Input
Data is acquired at the falling edge of CLK+ (pin 18) and the
digital equivalent of that data is available at the digital outputs
13 input clock cycles later for the DI and DQ output buses and
14 input clock cycles later for the DId and DQd output buses.
There is an additional internal delay called t
is available at the outputs. See the Timing Diagram. The AD-
C08D1000 will convert as long as the input clock signal is
present. The fully differential comparator design and the in-
novative design of the sample-and-hold amplifier, together
with self calibration, enables a very flat SINAD/ENOB re-
sponse beyond 1.0 GHz. The ADC08D1000 output data sig-
naling is LVDS and the output format is offset binary.
CAL_L
During the calibration cycle, the OR output may be active
as a result of the calibration algorithm. All data on the
output pins and the OR output are invalid during the
calibration cycle.
During the power-up calibration and during the on-
command calibration, all clocks are halted on chip,
including internal clocks and DCLK, while the input
termination resistor is trimmed to a value that is equal to
R
calibration portion of the calibration cycle. See 2.4.2 Self
Calibration for information on maintaining DCLK operation
during on-command calibration.
This external resistor is located between pin 32 and
ground. R
input termination resistor is trimmed to be 100 Ω. Because
R
and Hold amplifier, for the preamplifiers and for the
comparators, other values of R
The CalRun output is high whenever the calibration
procedure is running. This is true whether the calibration
is done at power-up or on-command.
EXT
EXT
clock cycles followed by t
/ 33. This is to reduce noise during the input resistor
is also used to set the proper current for the Track
EXT
must be 3300 Ω ±0.1%. With this value, the
CalDly
in the Converter Electrical Charac-
CAL_H
EXT
EXT
clock cycles.
should not be used.
EXT
is also used to set the
/ 33. This external
OD
CAL_H
before the data
EXT
clock cycles
CAL_L
EXT
must be
should
clock
CAL
in