ADC08D1000DEV NSC [National Semiconductor], ADC08D1000DEV Datasheet - Page 30

• Manufacturer Part Number: ADC08D1000DEV
• Description: High Performance, Low Power, Dual 8-Bit, 1 GSPS A/D Converter
• Manufacturer: NSC [National Semiconductor]

www.national.com
1.4.1 Note Regarding Extended Mode Offset Correction
When using the I or Q channel Offset Adjust registers, the
following information should be noted.
For offset values of +0000 0000 and -0000 0000, the actual
offset is not the same. By changing only the sign bit in this
case, an offset step in the digital output code of about 1/10th
of an LSB is experienced. This is shown more clearly in the
Figure below.
Bit 15
Bit 14
Bits 15:7
Bit 6:0
Bits 13:11 Coarse Adjust Magnitude. Each code value in
Bits 10:0 Must be set to 1b
Addr: Eh (1110b)
Addr: Fh (1111b)
(MSB)
(LSB)
D15
D15
D7
D7
IS
1
ADS
D14
D14
D6
D6
1
1
Input Select. When this bit is set to 0b the "I"
input is operated upon by both ADCs. When
this bit is set to 1b the "Q" input is operated on
by both ADCs.
POR State: 0b
Adjust Direction Select. When this bit is set to
0b, the programmed delays are applied to the
"I" channel sample clock while the "Q" channel
sample clock remains fixed. When this bit is
set to 1b, the programmed delays are applied
to the "Q" channel sample clock while the "I"
channel sample clock remains fixed.
POR State: 0b
this field delays either the "I" channel or the "Q"
channel sample clock (as determined by the
ADS bit) by approximately 20 picoseconds. A
value of 000b in this field causes zero
adjustment.
POR State: 000b
Fine Adjust Magnitude. Each code value in this
field delays either the "I" channel or the "Q"
channel sample clock (as determined by the
ADS bit of the DES Coarse Adjust Register) by
approximately 0.1 ps. A value of 0000 0000 0b
in this field causes zero adjustment. Note that
the amount of adjustment achieved with each
code will vary with the device conditions as
well as with the Coarse Adjustment value
chosen.
POR State: 0000 0000 0b
Must be set to 1b
D13
D13
D5
D5
1
1
DES Coarse Adjust
DES Fine Adjust
CAM
D12
D12
D4
D4
1
1
D11
D11
D3
D3
1
1
FAM
D10
D10
D2
D2
1
1
W only (0x07FF)
W only (0x007F)
1
D9
D1
D9
D1
1
1
1
D8
D0
D8
D0
1
1
1
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1.5 MULTIPLE ADC SYNCHRONIZATION
The ADC08D1000 has the capability to precisely reset its
sampling clock input to DCLK output relationship as deter-
mined by the user-supplied DCLK_RST pulse. This allows
multiple ADCs in a system to have their DCLK (and data) out-
puts transition at the same time with respect to the shared
CLK input that all the ADCs use for sampling.
The DCLK_RST signal must observe some timing require-
ments that are shown in Figure 6, Figure 7 and Figure 8 of the
Timing Diagrams. The DCLK_RST pulse must be of a mini-
mum width and its desertion edge must observe setup and
hold times with respect to the CLK input rising edge. These
times are specified in the AC Converter Electrical Character-
istics.
The DCLK_RST signal can be asserted asynchronous to the
input clock. If DCLK_RST is asserted, the DCLK output is held
in a designated state. The state in which DCLK is held during
the reset period is determined by the mode of operation (SDR/
DDR) and the setting of the Output Edge configuration pin or
bit. (Refer to Figure 6, Figure 7 and Figure 8 for the DCLK
reset state conditions). Therefore, depending upon when the
DCLK_RST signal is asserted, there may be a narrow pulse
on the DCLK line during this reset event. When the
DCLK_RST signal is de-asserted in synchronization with the
CLK rising edge, the next CLK falling edge synchronizes the
DCLK output with those of other ADC08D1000s in the sys-
tem. The DCLK output is enabled again after a constant delay
(relative to the input clock frequency) which is equal to the
CLK input to DCLK output delay (t
hibits this delay characteristic in normal operation.
The DCLK-RST pin should NOT be brought high while the
calibration process is running (while CalRun is high). Doing
so could cause a digital glitch in the digital circuitry, resulting
in corruption and invalidation of the calibration.
2.0 Applications Information
2.1 THE REFERENCE VOLTAGE
The voltage reference for the ADC08D1000 is derived from a
1.254V bandgap reference, a buffered version of which is
made available at pin 31, V
This output has an output current capability of ±100 μA and
should be buffered if more current than this is required.
The internal bandgap-derived reference voltage has a nomi-
nal value V
Section 1.1.4.
There is no provision for the use of an external reference volt-
age, but the full-scale input voltage can be adjusted through
FIGURE 10. Extended Mode Offset Behavior
IN
, as determined by the FSR pin and described in
BG
, for user convenience.
SD
). The device always ex-
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