ADC08D1000DEV NSC [National Semiconductor], ADC08D1000DEV Datasheet - Page 32

• Manufacturer Part Number: ADC08D1000DEV
• Description: High Performance, Low Power, Dual 8-Bit, 1 GSPS A/D Converter
• Manufacturer: NSC [National Semiconductor]

www.national.com
The Input impedance in the d.c. coupled mode (V
grounded) consists of a precision 100Ω resistor between V
+ and V
ground. In the a.c. coupled mode the input appears the same
except there is also a resistor of 50K between each analog
input pin and the V
Driving the inputs beyond full scale will result in a saturation
or clipping of the reconstructed output.
2.2.1 Handling Single-Ended Input Signals
There is no provision for the ADC08D1000 to adequately pro-
cess single-ended input signals. The best way to handle
single-ended signals is to convert them to differential signals
before presenting them to the ADC. The easiest way to ac-
complish single-ended to differential signal conversion is with
an appropriate balun-connected transformer, as shown in
Figure 13.
2.2.1.1 a.c. Coupled Input
The easiest way to accomplish single-ended a.c. Input to dif-
ferential a.c. signal is with an appropriate balun-connected
transformer, as shown in ?? F13.
The 100 Ohm external resistor placed across the output ter-
minals of the balun in parallel with the ADC08D1000's on-chip
100 Ohm resistor makes a 50 Ohms differential impedance
at the balun output. Or, 25 Ohms to virtual ground at each of
the balun output terminals.
Looking into the balun, the source sees the impedance of the
first coil in series with the impedance at the output of that coil.
Since the transformer has a 1:1 turns ratio, the impedance
across the first coil is exactly the same as that at the output
of the second coil, namely 25 Ohms to virtual ground. So, the
25 Ohms across the first coil in series with the 25 Ohms at its
output gives 50 Ohms total impedance to match the source.
2.2.2 Out Of Range (OR) Indication
When the conversion result is clipped the Out of Range output
is activated such that OR+ goes high and OR- goes low. This
output is active as long as accurate data on either or both of
the buses would be outside the range of 00h to FFh.
2.2.3 Full-Scale Input Range
As with all A/D Converters, the input range is determined by
the value of the ADC's reference voltage. The reference volt-
age of the ADC08D1000 is derived from an internal band-gap
reference. The FSR pin controls the effective reference volt-
age of the ADC08D1500 such that the differential full-scale
input range at the analog inputs is a normal amplitude with
the FSR pin high, or a reduced amplitude with FSR pin low as
defined by the specification V
Characteristics. Best SNR is obtained with FSR high, but bet-
ter distortion and SFDR are obtained with the FSR pin low.
FIGURE 13. Single-Ended to Differential Signal
IN
− and a capacitance from each of these inputs to
Conversion Using a Balun
CMO
potential.
IN
in the Converter Electrical
CMO
20097443
pin not
IN
32
The LMH6555 of Figure 12 is suitable for any Full Scale
Range.
2.3 THE CLOCK INPUTS
The ADC08D1000 has differential LVDS clock inputs, CLK+
and CLK-, which must be driven with an a.c. coupled, differ-
ential clock signal. Although the ADC08D1000 is tested and
its performance is guaranteed with a differential 1.0 GHz
clock, it typically will function well with input clock frequencies
indicated in the Converter Electrical Characteristics. The
clock inputs are internally terminated and biased. The input
clock signal must be capacitively coupled to the clock pins as
indicated in Figure 14.
Operation up to the sample rates indicated in the Converter
Electrical Characteristics is typically possible if the maximum
ambient temperatures indicated are not exceeded. Operating
at higher sample rates than indicated for the given ambient
temperature may result in reduced device reliability and prod-
uct lifetime. This is because of the higher power consumption
and die temperatures at high sample rates. Important also for
reliability is proper thermal management . See 2.6.2 Thermal
Management.
The differential input clock line pair should have a character-
istic impedance of 100Ω and (when using a balun), be termi-
nated at the clock source in that (100Ω) characteristic
impedance. The input clock line should be as short and as
direct as possible. The ADC08D1000 clock input is internally
terminated with an untrimmed 100Ω resistor.
Insufficient input clock levels will result in poor dynamic per-
formance. Excessively high input clock levels could cause a
change in the analog input offset voltage. To avoid these
problems, keep the input clock level within the range specified
in the Converter Electrical Characteristics.
The low and high times of the input clock signal can affect the
performance of any A/D Converter. The ADC08D1000 fea-
tures a duty cycle clock correction circuit which can maintain
performance over temperature even in DES mode. The ADC
will meet its performance specification if the input clock high
and low times are maintained within the range (20/80% ratio)
as specified in the Converter Electrical Characteristics.
High speed, high performance ADCs such as the AD-
C08D1000 require a very stable input clock signal with mini-
mum phase noise or jitter. ADC jitter requirements are defined
by the ADC resolution (number of bits), maximum ADC input
frequency and the input signal amplitude relative to the ADC
input full scale range. The maximum jitter (the sum of the jitter
from all sources) allowed to prevent a jitter-induced reduction
in SNR is found to be
FIGURE 14. Differential (LVDS) Input Clock Connection
t
J(MAX)
= (V
INFSR
/ V
IN(P-P)
) x (1/(2
20097447
(N+1)
x
π
x f
IN
))