ADC08D1000DEV NSC [National Semiconductor], ADC08D1000DEV Datasheet - Page 33

• Manufacturer Part Number: ADC08D1000DEV
• Description: High Performance, Low Power, Dual 8-Bit, 1 GSPS A/D Converter
• Manufacturer: NSC [National Semiconductor]

where t
V
full-scale range of the ADC, "N" is the ADC resolution in bits
and f
analog input.
Note that the maximum jitter described above is the arithmetic
sum of the jitter from all sources, including that in the ADC
input clock, that added by the system to the ADC input clock
and input signals and that added by the ADC itself. Since the
effective jitter added by the ADC is beyond user control, the
best the user can do is to keep the sum of the externally added
input clock jitter and the jitter added by the analog circuitry to
the analog signal to a minimum.
Input clock amplitudes above those specified in the Converter
Electrical Characteristics may result in increased input offset
voltage. This would cause the converter to produce an output
code other than the expected 127/128 when both input pins
are at the same potential.
2.4 CONTROL PINS
Six control pins (without the use of the serial interface) provide
a wide range of possibilities in the operation of the AD-
C08D1000 and facilitate its use. These control pins provide
Full-Scale Input Range setting, Self Calibration, Calibration
Delay, Output Edge Synchronization choice, LVDS Output
Level choice and a Power Down feature.
2.4.1 Full-Scale Input Range Setting
The input full-scale range can be selected with the FSR con-
trol input (pin 14) in the normal mode of operation. The is
specified as V
the extended control mode, the input full-scale range may be
programmed using the Full-Scale Adjust Voltage register.
See 2.2 THE ANALOG INPUT for more information.
2.4.2 Self Calibration
The ADC08D1000 self-calibration must be run to achieve
specified performance. The calibration procedure is run upon
power-up and can be run any time on command. The cali-
bration procedure is exactly the same whether there is an
input clock present upon power up or if the clock begins some
time after application of power. The CalRun output indicator
is high while a calibration is in progress. Note that DCLK out-
puts are not active during a calibration cycle, therefore it is not
recommended as a system clock.
2.4.2.1 Power-On Calibration
Power-on calibration begins after a time delay following the
application of power. This time delay is determined by the
setting of CalDly, as described in the Calibration Delay Sec-
tion, below.
The calibration process will be not be performed if the CAL
pin is high at power up. In this case, the calibration cycle will
not begin until the on-command calibration conditions are
met. The ADC08D1000 will function with the CAL pin held
high at power up, but no calibration will be done and perfor-
mance will be impaired. A manual calibration, however, may
be performed after powering up with the CAL pin high. See
2.4.2.2 On-Command Calibration.
The internal power-on calibration circuitry comes up in an un-
known logic state. If the input clock is not running at power up
and the power on calibration circuitry is active, it will hold the
analog circuitry in power down and the power consumption
will typically be less than 200 mW. The power consumption
will be normal after the clock starts.
IN(P-P)
IN
is the maximum input frequency, in Hertz, to the ADC
J(MAX)
is the peak-to-peak analog input signal, V
is the rms total of all jitter sources in seconds,
IN
in the Converter Electrical Characteristics. In
INFSR
is the
33
2.4.2.2 On-Command Calibration
On-command calibration may be run at any time in NORMAL
(non-DES) mode only. Do not run a calibration while operat-
ing the ADC in Auto DES Mode.
If the ADC is operating in Auto DES mode and a calibration
cycle is required then the controlling application should bring
the ADC into normal (non DES) mode before an On Com-
mand calibration is initiated. Once calibration has completed,
the ADC can be put back into Auto DES mode.
To initiate an on-command calibration, bring the CAL pin high
for a minimum of t
low for a minimum of t
CAL pin high upon power up will prevent execution of power-
on calibration until the CAL pin is low for a minimum of
t
another t
begin t
brought high. The CalRun signal should be monitored to de-
termine when the calibration cycle has completed.
The minimum t
are required to ensure that random noise does not cause a
calibration to begin when it is not desired. As mentioned in
Section 1.1.1 for best performance, a self calibration should
be performed 20 seconds or more after power up and repeat-
ed when the operating temperature changes significantly,
according to the particular system performance requirements.
ENOB drops slightly with increasing junction temperature,
and a self calibration eliminates the change. In the first ex-
ample, (see Figure 15) a sample clock of 1GSPS is used to
capture a full-scale 749MHz signal at the I-channel input as
the junction temperature (T
C with no intermediate calibration cycles. The vertical line at
125°C is the result of an on-command calibration cycle that
essentially eliminates the drop in ENOB. Of course, calibra-
tion cycles can be run more often, at smaller intervals of
temperature change, if system design specifications require
it. In the second example, (see Figure 16) the test method is
the same and the I-channel input signal is 249MHz. The vari-
ation in ENOB vs. T
example, and is again removed by an on-command calibra-
tion cycle at the maximum test temperature.
CAL_L
FIGURE 15. ENOB vs. Junction Temperature, 749 MHz
input clock cycles, then brought high for a minimum of
CAL_H
CAL_H
input clock cycles after the CAL pin is thus
CAL_H
input clock cycles. The calibration cycle will
CAL_H
J
and t
has a smaller range then the previous
CAL_L
input clock cycles after it has been
CAL_L
J
Input
) is increased from 65°C to 125°
input clock cycles. Holding the
input clock cycle sequences
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