ADC08D1000DEV NSC [National Semiconductor], ADC08D1000DEV Datasheet - Page 29

• Manufacturer Part Number: ADC08D1000DEV
• Description: High Performance, Low Power, Dual 8-Bit, 1 GSPS A/D Converter
• Manufacturer: NSC [National Semiconductor]

Bit 15:7
Bit 15:8
Bit 7
Bit 6:0
(MSB)
(MSB)
Addr: 3h (0011b)
Addr: Ah (1010b)
Addr: Bh (1011b)
(LSB)
(MSB)
(LSB)
Bits 6:0
Sign
D15
D15
D15
D7
D7
D7
Q-Channel Full-Scale Voltage Adjust
D14
D14
I-Channel Full-Scale Voltage Adjust
D14
D6
D6
D6
1
1
1
Full Scale Voltage Adjust Value. The input full-
scale voltage or gain of the I-Channel ADC is
adjusted linearly and monotonically with a 9 bit
data value. The adjustment range is ±20% of
the nominal 700 mV
0000 0000 0
1000 0000 0
Default Value
1111 1111 1
For best performance, it is recommended that
the value in this field be limited to the range of
0110 0000 0b to 1110 0000 0b. i.e., limit the
amount of adjustment to ±15%. The remaining
±5% headroom allows for the ADC's own full
scale variation. A gain adjustment does not
require ADC re-calibration.
POR State: 1000 0000 0b (no adjustment)
Must be set to 1b
Offset Value. The input offset of the Q-
Channel ADC is adjusted linearly and
monotonically by the value in this field. 00h
provides a nominal zero offset, while FFh
provides a nominal 45 mV of offset. Thus,
each code step provides about 0.176 mV of
offset.
POR State: 0000 0000 b
Sign bit. 0b gives positive offset, 1b gives
negative offset.
POR State: 0b
Must be set to 1b
D13
D13
D13
D5
D5
D5
1
1
1
Q-Channel Offset
Offset Value
D12
D12
D12
D4
D4
D4
1
1
1
Adjust Value
Adjust Value
D11
560mV
700mV
840mV
D11
D11
D3
D3
D3
1
P-P
1
1
differential value.
D10
D10
D10
P-P
P-P
P-P
D2
D2
D2
1
1
W only (0x807F)
W only (0x007F)
W only (0x807F)
1
D9
D1
D1
D9
D9
D1
1
1
1
(LSB)
D8
D0
D8
D0
D8
D0
1
1
1
29
Bit 15:7
Bits 6:0
Bit 15
Bit 14
Bits 13:0
Addr: Dh (1101b)
DEN ACP
D15
D7
1
D14
D6
1
Full Scale Voltage Adjust Value. The input full-
scale voltage or gain of the I-Channel ADC is
adjusted linearly and monotonically with a 9 bit
data value. The adjustment range is ±20% of
the nominal 700 mV
0000 0000 0
1000 0000 0
1111 1111 1
For best performance, it is recommended that
the value in this field be limited to the range of
0110 0000 0b to 1110 0000 0b. i.e., limit the
amount of adjustment to ±15%. The remaining
±5% headroom allows for the ADC's own full
scale variation. A gain adjustment does not
require ADC re-calibration.
POR State: 1000 0000 0b (no adjustment)
Must be set to 1b
DES Enable. Setting this bit to 1b enables the
Dual Edge Sampling mode. In this mode the
ADCs in this device are used to sample and
convert the same analog input in a time-
interleaved manner, accomplishing a
sampling rate of twice the input clock rate.
When this bit is set to 0b, the device operates
in the normal dual channel mode.
POR State: 0b
Automatic Clock Phase Control. (ACP) Setting
this bit to 1b enables the Automatic Clock
Phase Control. In this mode the DES Coarse
and Fine manual controls are disabled. A
phase detection circuit continually adjusts the
I and Q sampling edges to be 180 degrees out
of phase. When this bit is set to 0b, the sample
(input) clock delay between the I and Q
channels is set manually using the DES
Coarse and Fine Adjust registers. (See 2.4.5
Dual Edge Sampling for important application
information) Using the ACP Control option
is recommended over the manual DES
settings.
POR State: 0b
Must be set to 1b
D13
D5
1
1
DES Enable
D12
D4
1
1
D11
560mV
700mV
840mV
D3
1
1
P-P
differential value.
D10
P-P
P-P
P-P
D2
W only (0x3FFF)
1
1
D9
D1
1
1
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D8
D0
1
1