ADC08D1000DEV NSC [National Semiconductor], ADC08D1000DEV Datasheet - Page 34

• Manufacturer Part Number: ADC08D1000DEV
• Description: High Performance, Low Power, Dual 8-Bit, 1 GSPS A/D Converter
• Manufacturer: NSC [National Semiconductor]

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2.4.2.3 Calibration Delay
The CalDly input (pin 127) is used to select one of two delay
times after the application of power to the start of calibration,
as described in Section 1.1.1. The calibration delay values
allow the power supply to come up and stabilize before cali-
bration takes place. With no delay or insufficient delay, cali-
bration would begin before the power supply is stabilized at
its operating value and result in non-optimal calibration coef-
ficients. If the PD pin is high upon power-up, the calibration
delay counter will be disabled until the PD pin is brought low.
Therefore, holding the PD pin high during power up will further
delay the start of the power-up calibration cycle. The best
setting of the CalDly pin depends upon the power-on settling
time of the power supply.
Note that the calibration delay selection is not possible in the
Extended Control mode and the short delay time is used.
2.4.3 Output Edge Synchronization
DCLK signals are available to help latch the converter output
data into external circuitry. The output data can be synchro-
nized with either edge of these DCLK signals. That is, the
output data transition can be set to occur with either the rising
edge or the falling edge of the DCLK signal, so that either
edge of that DCLK signal can be used to latch the output data
into the receiving circuit.
When OutEdge (pin 4) is high, the output data is synchronized
with (changes with) the rising edge of the DCLK+ (pin 82).
When OutEdge is low, the output data is synchronized with
the falling edge of DCLK+.
At the very high speeds of which the ADC08D1000 is capable,
slight differences in the lengths of the DCLK and data lines
can mean the difference between successful and erroneous
data capture. The OutEdge pin is used to capture data on the
DCLK edge that best suits the application circuit and layout.
2.4.4 LVDS Output Level Control
The output level can be set to one of two levels with OutV
(pin3). The strength of the output drivers is greater with OutV
high. With OutV low there is less power consumption in the
output drivers, but the lower output level means decreased
noise immunity.
For short LVDS lines and low noise systems, satisfactory per-
formance may be realized with the OutV input low. If the LVDS
FIGURE 16. ENOB vs. Junction Temperature, 249 MHz
Input
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34
lines are long and/or the system in which the ADC08D1000
is used is noisy, it may be necessary to tie the OutV pin high.
2.4.5 Dual Edge Sampling
The Dual Edge Sampling (DES) feature causes one of the two
input pairs to be routed to both ADCs. The other input pair is
deactivated. One of the ADCs samples the input signal on one
input clock edge (duty cycle corrected), the other samples the
input signal on the other input clock edge (duty cycle correct-
ed). The result is a 1:4 demultiplexed output with a sample
rate that is twice the input clock frequency.
To use this feature in the non-enhanced control mode, allow
pin 127 to float and the signal at the "I" channel input will be
sampled by both converters. The Calibration Delay will then
only be a short delay.
In the enhanced control mode, either input may be used for
dual edge sampling. See 1.1.5.1 Dual-Edge Sampling.
IMPORTANT NOTES :
1) For the Extended Control Mode - When using the Auto-
matic Clock Phase Control feature in dual edge sampling
mode, it is important that the automatic phase control is dis-
abled (set bit 14 of DES Enable register Dh to 0) before the
ADC is powered up. Not doing so may cause the device not
to wake up from the power down state.
2) For the Non-Extended Control Mode - When the AD-
C08D1000 is powered up and DES mode is required, ensure
that pin 127 (CalDly/DES/SCS) is initially pulled low during or
after the power up sequence. The pin can then be allowed to
float or be tied to V
sure that the part enters the DES mode correctly.
3) The automatic phase control should also be disabled if the
input clock is interrupted or stopped for any reason. This is
also the case if a large abrupt change in the clock frequency
occurs.
4) If a calibration of the ADC is required in Auto DES mode,
the device must be returned to the Normal Mode of operation
before performing a calibration cycle. Once the Calibration
has been completed, the device can be returned to the Auto
DES mode and operation can resume.
2.4.6 Power Down Feature
The Power Down pins (PD and PDQ) allow the ADC08D1000
to be entirely powered down (PD) or the "Q" channel to be
powered down and the "I" channel to remain active. See 1.1.7
Power Down for details on the power down feature.
The digital data (+/-) output pins are put into a high impedance
state when the PD pin for the respective channel is high. Upon
return to normal operation, the pipeline will contain meaning-
less information and must be flushed.
If the PD input is brought high while a calibration is running,
the device will not go into power down until the calibration
sequence is complete. However, if power is applied and PD
is already high, the device will not begin the calibration se-
quence until the PD input goes low. If a manual calibration is
requested while the device is powered down, the calibration
will not begin at all. That is, the manual calibration input is
completely ignored in the power down state.
2.5 THE DIGITAL OUTPUTS
The ADC08D1000 demultiplexes the output data of each of
the two ADCs on the die onto two LVDS output buses (total
of four buses, two for each ADC). For each of the two con-
verters, the results of successive conversions started on the
odd falling edges of the CLK+ pin are available on one of the
two LVDS buses, while the results of conversions started on
the even falling edges of the CLK+ pin are available on the
A
/ 2 to enter the DES mode. This will en-