ADC08D1000DEV NSC [National Semiconductor], ADC08D1000DEV Datasheet - Page 3

• Manufacturer Part Number: ADC08D1000DEV
• Description: High Performance, Low Power, Dual 8-Bit, 1 GSPS A/D Converter
• Manufacturer: NSC [National Semiconductor]

Pin Functions
Pin No.
Pin Descriptions and Equivalent Circuits
15
26
30
29
14
3
4
OutEdge / DDR /
OutV / SCLK
DCLK_RST/
DCLK_RST-
FSR/ECE
Symbol
SDATA
PDQ
CAL
PD
Equivalent Circuit
3
Output Voltage Amplitude and Serial Interface Clock. Tie this pin
high for normal differential DCLK and data amplitude. Ground this
pin for a reduced differential output amplitude and reduced power
consumption. See1.1.6 The LVDS Outputs. When the extended
control mode is enabled, this pin functions as the SCLK input which
clocks in the serial data. See 1.2 NORMAL/EXTENDED
CONTROL for details on the extended control mode. See 1.3 THE
SERIAL INTERFACE for description of the serial interface.
DCLK Edge Select, Double Data Rate Enable and Serial Data
Input. This input sets the output edge of DCLK+ at which the output
data transitions. (See 1.1.5.2 OutEdge Setting). When this pin is
floating or connected to 1/2 the supply voltage, DDR clocking is
enabled. When the extended control mode is enabled, this pin
functions as the SDATA input. See 1.2 NORMAL/EXTENDED
CONTROL for details on the extended control mode. See 1.3 THE
SERIAL INTERFACE for description of the serial interface.
DCLK Reset. A positive pulse on this pin is used to reset and
synchronize the DCLK outs of multiple converters. See 1.5
MULTIPLE ADC SYNCHRONIZATION for detailed description.
Power Down Pins. A logic high on the PD pin puts the entire device
into the Power Down Mode.
Calibration Cycle Initiate. A minimum t
low followed by a minimum of t
pin initiates the self calibration sequence. See 2.4.2 Self
Calibration for an overview of self-calibration and 2.4.2.2 On-
Command Calibration for a description of on-command
calibration.
A logic high on the PDQ pin puts only the "Q" ADC into the Power
Down mode.
Full Scale Range Select and Extended Control Enable. In non-
extended control mode, a logic low on this pin sets the full-scale
differential input range to a reduced V
on this pin sets the full-scale differential input range to a higher
V
the extended control mode, whereby the serial interface and
control registers are employed, allow this pin to float or connect it
to a voltage equal to V
CONTROL for information on the extended control mode.
IN
input level. See Converter Electrical Characteristics. To enable
A
/2. See 1.2 NORMAL/EXTENDED
Description
CAL_H
input clock cycles high on this
CAL_L
IN
input level . A logic high
input clock cycles logic
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