ADC08D1000DEV NSC [National Semiconductor], ADC08D1000DEV Datasheet - Page 25

• Manufacturer Part Number: ADC08D1000DEV
• Description: High Performance, Low Power, Dual 8-Bit, 1 GSPS A/D Converter
• Manufacturer: NSC [National Semiconductor]

1.1.3 Control Modes
Much of the user control can be accomplished with several
control pins that are provided. Examples include initiation of
the calibration cycle, power down mode and full scale range
setting. However, the ADC08D1000 also provides an Extend-
ed Control mode whereby a serial interface is used to access
register-based control of several advanced features. The Ex-
tended Control mode is not intended to be enabled and
disabled dynamically. Rather, the user is expected to employ
either the normal control mode or the Extended Control mode
at all times. When the device is in the Extended Control mode,
pin-based control of several features is replaced with register-
based control and those pin-based controls are disabled.
These pins are OutV (pin 3), OutEdge/DDR (pin 4), FSR (pin
14) and CalDly/DES (pin 127). See 1.2 NORMAL/EXTEND-
ED CONTROL for details on the Extended Control mode.
1.1.4 The Analog Inputs
The ADC08D1000 must be driven with a differential input sig-
nal. Operation with a single-ended signal is not recommend-
ed. It is important that the inputs either be a.c. coupled to the
inputs with the V
V
to the V
used.
Two full-scale range settings are provided with pin 14 (FSR).
The input full-scale range is programmable in the normal
mode by setting a level on pin 14 (FSR) as defined in by the
specification V
The full-scale range setting operates equally on both ADCs.
In the Extended Control mode, programming the Input Full-
Scale Voltage Adjust register allows the input full-scale range
to be adjusted as described in ??1.4 and ??2.2.
1.1.5 Clocking
The ADC08D1000 must be driven with an a.c. coupled, dif-
ferential clock signal. Section 2.3 describes the use of the
clock input pins. A differential LVDS output clock is available
for use in latching the ADC output data into whatever device
is used to receive the data.
The ADC08D1000 offers two options for input and output
clocking. These options include a choice of Dual Edge Sam-
pling (DES) or "interleaved mode" where the ADC08D1000
CMO
* Note: In DES + normal mode, only the I Channel is sampled. In DES + extended control mode, I or Q channel can be
sampled.
sourced with respect to fall
pin left floating. An input common mode voltage equal
Data Outputs (Always
CMO
output must be provided when d.c. coupling is
of DCLK)
IN
DQd
DId
DQ
DI
CMO
in the Converter Electrical Characteristics.
pin grounded, or d.c. coupled with the
TABLE 1. Input Channel Samples Produced at Data Outputs
"I" Input Sampled with Fall of
CLK 13 cycles earlier.
"I" Input Sampled with Fall of
CLK 14 cycles earlier.
"Q" Input Sampled with Fall of
CLK 13 cycles earlier.
"Q" Input Sampled with Fall of
CLK 14 cycles after being
sampled.
Normal Sampling Mode
25
"I" Input Sampled with Fall of
CLK 13 cycles earlier.
"I" Input Sampled with Fall of
CLK 14 cycles earlier.
"I" Input Sampled with Rise of
CLK 13.5 cycles earlier.
"I" Input Sampled with Rise of
CLK 14.5 cycles earlier.
performs as a single device converting at twice the input clock
rate, a choice of which DCLK edge the output data transitions
on, and a choice of Single Data Rate (SDR) or Double Data
Rate (DDR) outputs.
The ADC08D1000 also has the option to use a duty cycle
corrected clock receiver as part of the input clock circuit. This
feature is enabled by default and provides improved ADC
clocking especially in the Dual-Edge Sampling mode (DES).
This circuitry allows the ADC to be clocked with a signal
source having a duty cycle ratio of 80 / 20 % (worst case) for
both the normal and the Dual Edge Sampling modes.
1.1.5.1 Dual-Edge Sampling
The DES mode allows one of the ADC08D1000's inputs (I or
Q Channel) to be sampled by both ADCs. One ADC samples
the input on the positive edge of the input clock and the other
ADC samples the same input on the other edge of the input
clock. A single input is thus sampled twice per input clock cy-
cle, resulting in an overall sample rate of twice the input clock
frequency, or 2 GSPS with a 1 GHz input clock.
In this mode the outputs are interleaved such that the data is
effectively demultiplexed 1:4. Since the sample rate is dou-
bled, each of the 4 output buses have a 500 MSPS output rate
with a 1 GHz input clock. All data is available in parallel. The
four bytes of parallel data that are output with each clock is in
the following sampling order, from the earliest to the latest:
DQd, DId, DQ, DI. Table 1 indicates what the outputs repre-
sent for the various sampling possibilities.
In the non-extended mode of operation only the "I" input can
be sampled in the DES mode. In the extended mode of op-
eration the user can select which input is sampled.
The ADC08D1000 also includes an automatic clock phase
background calibration feature which can be used in DES
mode to automatically and continuously adjust the clock
phase of the I and Q channel. This feature removes the need
to adjust the clock phase setting manually and provides opti-
mal Dual-Edge Sampling ENOB performance.
IMPORTANT NOTE: The background calibration feature in
DES mode does not replace the requirement for On-Com-
mand Calibration which should be run before entering DES
mode, or if a large swing in ambient temperature is experi-
enced by the device.
I-Channel Selected
Dual-Edge Sampling Mode (DES)
"Q" Input Sampled with Fall of
CLK 13 cycles earlier.
"Q" Input Sampled with Fall of
CLK 14 cycles earlier.
"Q" Input Sampled with Rise
of CLK 13.5 cycles earlier.
"Q" Input Sampled with Rise
of CLK 14.5 cycles earlier.
Q-Channel Selected *
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