ADC08D1000DEV NSC [National Semiconductor], ADC08D1000DEV Datasheet - Page 37

• Manufacturer Part Number: ADC08D1000DEV
• Description: High Performance, Low Power, Dual 8-Bit, 1 GSPS A/D Converter
• Manufacturer: NSC [National Semiconductor]

2.9.1 Non-Extended Control Mode Operation
Non-extended control mode operation means that the Serial
Interface is not active and all controllable functions are con-
trolled with various pin settings. That is, the full-scale range,
single-ended or differential input, the power on calibration de-
lay, the output voltage and the input coupling (a.c. or d.c.).
The non-extended control mode is used by setting pin 14 high
or low, as opposed to letting it float. Table 6 indicates the pin
functions of the ADC08D1000 in the non-extended control
mode.
Pin 3 can be either high or low in the non-extended control
mode. Pin 14 must not be left floating to select this mode. See
1.2 NORMAL/EXTENDED CONTROL for more information.
Pin 4 can be high or low or can be left floating in the non-
extended control mode. In the non-extended control mode,
pin 4 high or low defines the edge at which the output data
transitions. See 2.4.3 Output Edge Synchronization for more
information. If this pin is floating, the output clock (DCLK) is a
DDR (Double Data Rate) clock (see 1.1.5.3 Double Data
Rate) and the output edge synchronization is irrelevant since
data is clocked out on both DCLK edges.
Pin 127 in the non-extended control mode sets the calibration
delay. Pin 127 is not designed to remain floating.
2.10 COMMON APPLICATION PITFALLS
Driving the inputs (analog or digital) beyond the power
supply rails. For device reliability, no input should go more
than 150 mV below the ground pins or 150 mV above the
TABLE 6. Non-Extended Control Mode Operation
127
Pin
TABLE 7. Extended Control Mode Operation
14
3
4
127
Pin
3
4
CalDly Short CalDly Long
Reduced V
OutEdge =
Reduced
(Pin 14 High or Low)
Low
Neg
V
(Pin 14 Floating)
SCS (Serial Interface Chip Select)
OD
IN
SDATA (Serial Data)
SCLK (Serial Clock)
Normal V
Normal V
OutEdge =
Function
High
Pos
OD
IN
Control Mode
Extended
Floating
DDR
n/a
n/a
37
supply pins. Exceeding these limits on even a transient basis
may not only cause faulty or erratic operation, but may impair
device reliability. It is not uncommon for high speed digital
circuits to exhibit undershoot that goes more than a volt below
ground. Controlling the impedance of high speed lines and
terminating these lines in their characteristic impedance
should control overshoot.
Care should be taken not to overdrive the inputs of the AD-
C08D1000. Such practice may lead to conversion inaccura-
cies and even to device damage.
Incorrect analog input common mode voltage in the d.c.
coupled mode. As discussed in sections 1.1.4 and 2.2, the
Input common mode voltage must remain within 50 mV of the
V
must also be tracked. Distortion performance will be degrad-
ed if the input common mode voltage is more than 50 mV from
V
Using an inadequate amplifier to drive the analog input.
Use care when choosing a high frequency amplifier to drive
the ADC08D1000 as many high speed amplifiers will have
higher distortion than will the ADC08D1000, resulting in over-
all system performance degradation.
Driving the V
mentioned in Section 2.1, the reference voltage is intended to
be fixed to provide one of two different full-scale values (650
mV
the full scale value, but can be used to change the LVDS
common mode voltage from 0.8V to 1.2V by tying the V
to V
Driving the clock input with an excessively high level
signal. The ADC input clock level should not exceed the level
described in the Operating Ratings Table or the input offset
could change.
Inadequate input clock levels. As described in Section 2.3,
insufficient input clock levels can result in poor performance.
Excessive input clock levels could result in the introduction of
an input offset.
Using a clock source with excessive jitter, using an ex-
cessively long input clock signal trace, or having other
signals coupled to the input clock signal trace. This will
cause the sampling interval to vary, causing excessive output
noise and a reduction in SNR performance.
Failure to provide adequate heat removal. As described in
Section 2.6.2, it is important to provide adequate heat removal
to ensure device reliability. This can be done either with ad-
equate air flow or the use of a simple heat sink built into the
board. The backside pad should be grounded for best perfor-
mance.
CMO
CMO
P-P
A
.
.
output , which has a variability with temperature that
and 870 mV
BG
pin to change the reference voltage. As
P-P
). Over driving this pin will not change
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BG
pin