ADC08D1000DEV NSC [National Semiconductor], ADC08D1000DEV Datasheet - Page 27

• Manufacturer Part Number: ADC08D1000DEV
• Description: High Performance, Low Power, Dual 8-Bit, 1 GSPS A/D Converter
• Manufacturer: NSC [National Semiconductor]

The default state of the Extended Control Mode is set upon
power-on reset (internally performed by the device) and is
shown in Table 3.
1.3 THE SERIAL INTERFACE
The 3-pin serial interface is enabled only when the device is
in the Extended Control mode. The pins of this interface are
Dual Edge Sampling (DES)
LVDS Output Amplitude
SDR or DDR Clocking
SDR or DDR Clocking
DDR Clock Phase
SDR Data transitions with rising or
falling DCLK edge
LVDS output level
Power-On Calibration Delay
Full-Scale Range
Input Offset Adjust
Dual Edge Sampling Selection
Dual Edge Sampling Input
Channel Selection
DES Sampling Clock Adjustment
Input Offset Adjust
TABLE 3. Extended Control Mode Operation
DDR Clock Phase
Calibration Delay
Full-Scale Range
Feature
Feature
(Pin 14 Floating)
Extended Control Mode
Data changes with DCLK
700 mV nominal for both
No adjustment for either
Normal amplitude
edge (0° phase)
DDR Clocking
Default State
(710 mV
Not enabled
Short Delay
channels
channel
DDR Clocking selected with pin 4
floating. SDR clocking selected when pin
4 not floating.
Not Selectable (0° Phase Only)
SDR Data transitions with rising edge of
DCLK+ when pin 4 is high and on falling
edge when low.
Normal differential data and DCLK
amplitude selected when pin 3 is high
and reduced amplitude selected when
low.
Short delay selected when pin 127 is low
and longer delay selected when high
Options (650 mV
selected with pin 14. Selected range
applies to both channels.
Not possible
Enabled with pin 127
Only I-Channel Input can be used
The Clock Phase is adjusted
automatically
P-P
TABLE 2. Features and modes
Normal Control Mode
)
P-P
or 870 mV
27
Serial Clock (SCLK), Serial Data (SDATA) and Serial Inter-
face Chip Select (SCS) Eight write only registers are acces-
sible through this serial interface.
SCS: This signal should be asserted low while accessing a
register through the serial interface. Setup and hold times with
respect to the SCLK must be observed.
SCLK: Serial data input is accepted with the rising edge of
this signal. There is no minimum frequency requirement for
SCLK.
SDATA: Each register access requires a specific 32-bit pat-
tern at this input. This pattern consists of a header, register
address and register value. The data is shifted in MSB first.
Setup and hold times with respect to the SCLK must be ob-
served. See the Timing Diagram.
Each Register access consists of 32 bits, as shown in Figure
5 of the Timing Diagrams. The fixed header pattern is 0000
0000 0001 (eleven zeros followed by a 1). The loading se-
quence is such that a "0" is loaded first. These 12 bits form
the header. The next 4 bits are the address of the register that
is to be written to and the last 16 bits are the data written to
the addressed register. The addresses of the various regis-
ters are indicated in Table 4.
Refer to the Register Description (Section 1.4) for information
on the data to be written to the registers.
Subsequent register accesses may be performed immediate-
ly, starting with the 33rd SCLK. This means that the SCS input
P-P
)
Selected with nDE in the Configuration
Register (1h; bit-10). When the device is
in DDR mode, address 1h, bit-8 must be
set to 0b.
Selected with DCP bit in the
Configuration Register (1h; bit-11).
Selected with OE in the Configuration
Register (1h; bit-8).
Selected with the OV in the
Configuration Register (1h; bit-9).
Short delay only.
Up to 512 step adjustments over a
nominal range specified in ??1.4.
Selected using the Input Full-Scale
Adjust register (3h; bits-7 thru 15).
512 steps of adjustment using the Input
Offset register (2h; bits-7 thru 15) as
specified in ??1.4
Enabled through DES Enable Register.
Either I- or Q-Channel input may be
sampled by both ADCs.
Automatic Clock Phase control can be
selected by setting bit 14 in the DES
Enable register (Dh). The clock phase
can also be adjusted manually through
the Coarse & Fine registers (Eh and Fh).
Extended Control Mode
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