ADSP-BF542 AD [Analog Devices], ADSP-BF542 Datasheet
ADSP-BF542
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ADSP-BF542 Summary of contents
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... Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. • ADSP-BF542/BF544/BF547/BF548/BF549 PERIPHERALS High-Speed USB On-the-Go (OTG) with Integrated PHY SD/SDIO Controller ATA/ATAPI-6 Controller ...
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... ADSP-BF542/4/7/8/9 TABLE OF CONTENTS General Description ................................................. 3 Low-Power Architecture ......................................... 4 System Integration ................................................ 4 ADSP-BF542/4/7/8/9 Processor Peripherals ................ 4 Blackfin Processor Core .......................................... 4 Memory Architecture ............................................ 5 DMA Controllers ................................................ 10 Real-Time Clock ................................................. 11 Watchdog Timer ................................................ 12 Timers ............................................................. 12 Up/Down Counter and Thumbwheel Interface .......... 12 Serial Ports (SPORTs) .......................................... 12 Serial Peripheral Interface (SPI) Ports ...................... 13 UART Ports (UARTs) .......................................... 13 Controller Area Network (CAN) ............................ 13 TWI Controller Interface ...
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... Keypad Interface MXVR GPIOs CAN on the ADSP-BF544 and ADSP-BF542 is only available on automotive grade devices. 128 128 128 64 – 533 600 600 533 600 Rev. PrG | Page December 2007 ADSP-BF542/4/7/8/9 Table 2. ...
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... SD/SDIO controller, a real-time clock, a watchdog timer, LCD controller, and multiple enhanced parallel peripheral interfaces. ADSP-BF542/4/7/8/9 PROCESSOR PERIPHERALS The ADSP-BF542/4/7/8/9 processor contains a rich set of peripherals connected to the core via several high bandwidth buses, providing flexibility in system configuration as well as excellent overall system performance (see ...
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... R1.H R1.L R0.H R0.L MEMORY ARCHITECTURE The ADSP-BF542/4/7/8/9 processor views memory as a single unified 4G byte address space, using 32-bit addresses. All The architecture provides three modes of operation: user mode, supervisor mode, and emulation mode. User mode has restricted access to certain system resources, thus providing a protected software environment, while supervisor mode has unrestricted access to the system and core resources ...
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... This memory map applies to all ADSP-BF542/4/7/8/9 processors, except for L2 memory population. ADSP-BF544 includes 64K Byte of L2 memory: 0xFEB0 0000 - 0xFEB0 FFFF. ADSP-BF542 includes no L2 memory. See also Internal (On-Chip) Memory The ADSP-BF542/4/7/8/9 processor has several blocks of on- chip memory providing high-bandwidth access to the core. ...
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... The MMRs are accessible only in supervisor mode and appear as reserved space to on-chip peripherals. Booting The ADSP-BF542/4/7/8/9 processor contains a small on-chip boot kernel, which configures the appropriate peripheral for booting. If the ADSP-BF542/4/7/8/9 processor is configured to Rev. PrG | Page December 2007 ADSP-BF542/4/7/8/9 ...
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... When an event is triggered, the state of the processor is saved on the supervisor stack. The ADSP-BF542/4/7/8/9 processor event controller consists of two stages, the core event controller (CEC) and the system interrupt controller (SIC). The core event controller works with the system interrupt controller to prioritize and control all sys- tem events ...
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... Timer 0 IRQ IVG11 4 Timer 1 IRQ IVG11 4 Timer 2 IRQ IVG11 4 Timer 3 IRQ IVG7 0 Timer 4 IRQ IVG7 0 Timer 5 IRQ IVG7 0 Timer 6 IRQ Rev. PrG | Page December 2007 ADSP-BF542/4/7/8/9 IRQ GP IRQ Core ID (at Reset) IRQ ID 57 IVG7 0 58 IVG7 0 59 IVG7 0 60 IVG7 0 61 ...
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... Pin IRQ 3 (PINT3) 95 Event Control The ADSP-BF542/4/7/8/9 processor provides the user with a very flexible mechanism to control the processing of events. In the CEC, three registers are used to coordinate and control events. Each register is 16 bits wide: • CEC interrupt latch register (ILAT). The ILAT register indicates when events have been latched ...
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... Host DMA Port Interface The Host DMA port (HOSTDP) facilitates a host device exter- nal to the ADSP-BF542/4/7/8 DMA master and transfer data back and forth. The host device always masters the transactions and the processor is always a DMA slave device. ...
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... SCLK TIMERS There are up to two timer units in the ADSP-BF542/4/7/8/9 processors. One unit provides eight general-purpose program- mable timers and the other unit provides three. Each timer has an external pin that can be configured either as a Pulse Width Modulator (PWM) or timer output input to clock the timer mechanism for measuring pulse widths and peri- ods of external events ...
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... Data Association (IrDA®) Serial Infrared Physical Layer Link Specification (SIR) protocol. CONTROLLER AREA NETWORK (CAN) The ADSP-BF542/4/9 processor offers up to two CAN control- lers that are communication controllers that implement the Controller Area Network (CAN) 2.0B (active) protocol. This protocol is an asynchronous communications protocol used in both industrial and automotive control systems ...
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... Pin Interrupts Due to its large number of port pins, the ADSP-BF542/4/7/8/9 processors introduce a new scheme to manage pin interrupts. Every port pin can request interrupts in either an edge-sensitive or a level-sensitive manner with programmable polarity. Inter- rupt functionality is decoupled from GPIO operation ...
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... Lockbox tures include: • OTP memory • Unique chip ID • Code authentication • Secure mode of operation 1 Lockbox is a trademark of Analog Devices, Inc. Rev. PrG | Page December 2007 ADSP-BF542/4/7/8 secure technology. Key fea- ...
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... Control of clocking to each 1 MOST is a registered trademark of Standard Microsystems, Corp. of the ADSP-BF542/4/7/8/9 processor peripherals also reduces power consumption. See settings for each mode. Full-On Operating Mode – Maximum Performance In the full-on mode, the PLL is enabled and is not bypassed, providing capability for maximum operational frequency ...
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... The use of multiple power domains maximizes flexibility, while maintaining compliance with industry standards and conventions. By isolating the inter- nal logic of the ADSP-BF542/4/7/8/9 processor into its own power domain, separate from the RTC and other I/O, the pro- cessor can take advantage of dynamic power management, without affecting the RTC or other I/O devices ...
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... ADSP-BF542/4/7/8/9 shown in Figure 6. A parallel-resonant, fundamental frequency, microprocessor-grade crystal is connected across the CLKIN and XTAL pins. The on-chip resistance between CLKIN and the XTAL pin is in the 500 kΩ range. Further parallel resistors are typically not recommended. The two capacitors and the series ...
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... BOOTING MODES The ADSP-BF542/4/7/8/9 processor has many mechanisms (listed in Table 9) for automatically loading internal and exter- nal memory after a reset. The boot mode is defined by four BMODE input pins dedicated to this purpose. There are two categories of boot modes: In master boot modes the processor actively loads data from parallel or serial memories ...
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... ADSP-BF542/4/7/8/9 0x0811 is used. Unless, altered by OTP settings an I memory that takes two address bytes is assumed. Develop- ment tools ensure that data that is booted to memories that cannot be accessed by the Blackfin core is written to inter- mediate storage place and then copied to final destination via Memory DMA. ...
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... The boot ROM also features C-callable function entries that can be called by the user application at run time. This enables sec- ond-stage boot or boot management schemes to be implemented with ease. Rev. PrG | Page December 2007 ADSP-BF542/4/7/8/9 ...
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... Frequently used instructions are encoded in 16 bits. DEVELOPMENT TOOLS The ADSP-BF542/4/7/8/9 processor is supported with a com- plete set of CROSSCORE® software and hardware development tools, including Analog Devices emulators and VisualDSP++® development environment. The same emulator hardware that supports other Blackfin processors also fully emulates the ADSP-BF542/4/7/8/9 processor ...
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... Preliminary Technical Data PIN DESCRIPTIONS ADSP-BF542/4/7/8/9 processor pin multiplexing scheme is listed in Table 11 and the pin definitions are listed in Table 11. Pin Multiplexing Primary Pin First Peripheral Function Function (Number Pins) , Port A GPIO (16 pins) SPORT2 (8 pins) SPORT3 (8 pins) Port B GPIO (15 pins) TWI1 (2 pins) ...
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... All Port connections always power up as inputs for some period of time and require resistive termination to a safe condition if used as outputs in the system total of 32 interrupts at once are available from Ports C through J, configurable in byte-wide blocks. ADSP-BF542/4/7/8/9 processor pin definitions are listed in Table 12. To see the pin multiplexing scheme, see ...
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... I/O GPIO/UART3 Receive/Alternate Capture Input 3 I/O GPIO/SPI2 Slave Select Input/Timer 0 I/O GPIO/SPI2 Slave Select Enable 1/Timer 1 I/O GPIO/SPI2 Slave Select Enable 2/Timer 2 I/O GPIO/SPI2 Slave Select Enable 3/Timer 3/Boot Host Wait I/O GPIO/SPI2 Clock I/O GPIO/SPI2 Master Out Slave In I/O GPIO/SPI2 Master In Slave Out Rev. PrG | Page December 2007 ADSP-BF542/4/7/8/9 ...
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... ADSP-BF542/4/7/8/9 Table 12. Pin Descriptions (Continued) Pin Name Port C: GPIO/SPORT0/SD Controller/MXVR (MOST) PC0/TFS0 PC1/DT0SEC/MMCLK PC2/DT0PRI PC3/TSCLK0 PC4/RFS0 PC5/DR0SEC/MBCLK PC6/DR0PRI PC7/RSCLK0 PC8/SD_D0 PC9/SD_D1 PC10/SD_D2 PC11/SD_D3 PC12/SD_CLK PC13/SD_CMD Port D: GPIO/EPPI0–2/SPORT 1/Keypad/Host DMA PD0/PPI1_D0/HOST_D8/ TFS1/PPI0_D18 PD1/PPI1_D1/HOST_D9/ DT1SEC/PPI0_D19 PD2/PPI1_D2/HOST_D10/ DT1PRI/PPI0_D20 PD3/PPI1_D3/HOST_D11/ TSCLK1/PPI0_D21 PD4/PPI1_D4 / HOST_D12/RFS1/PPI0_D22 ...
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... I/O GPIO/EPPI0 Data/Alternate ATAPI Data I/O GPIO/EPPI0 Data/Alternate ATAPI Data I/O GPIO/EPPI0 Data/Alternate ATAPI Data I/O GPIO/EPPI0 Data/Alternate ATAPI Data I/O GPIO/EPPI0 Data/Alternate ATAPI Data I/O GPIO/EPPI0 Data/Alternate ATAPI Data I/O GPIO/EPPI0 Data/Alternate ATAPI Data I/O GPIO/EPPI0 Data/Alternate ATAPI Data I/O GPIO/EPPI0 Data/Alternate ATAPI Data Rev. PrG | Page December 2007 ADSP-BF542/4/7/8/9 ...
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... ADSP-BF542/4/7/8/9 Table 12. Pin Descriptions (Continued) Pin Name Port G: GPIO / EPPI0 / SPI1 / EPPI2 / Up-Down Counter / CAN0–1 / Host DMA/ MXVR (MOST) PG0/PPI0_CLK/TMRCLK PG1/PPI0_FS1 4 PG2/PPI0_FS2/ATAPI_A0A 4 PG3/PPI0_D16/ATAPI_A1A 4 PG4/PPI0_D17/ATAPI_A2A PG5/SPI1SEL1/HOST_CE/PPI2_FS2/ CZM PG6/SPI1SEL2/HOST_RD/ PPI2_FS1 PG7/SPI1SEL3/HOST_WR/ PPI2_CLK PG8/SPI1SCK PG9/SPI1MISO PG10/SPI1MOSI PG11/SPI1SS/MTXON PG12/CAN0TX PG13/CAN0RX/TACI4 PG14/CAN1TX PG15/CAN1RX/TACI5 Port H: GPIO/AMC / EXTDMA / UART1 / EPPI0–2 / ATAPI Interface / Up-Down Counter /TMR8-10/ Host DMA / MXVR (MOST) ...
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... I/O DDR Data Strobe O DDR Data Mask for Reads and Writes O DDR Output Clock O DDR Complementary Output Clock O DDR Chip Selects O DDR Clock Enable O DDR Row Address Strobe O DDR Column Address Strobe O DDR Write Enable Rev. PrG | Page December 2007 ADSP-BF542/4/7/8/9 ...
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... ADSP-BF542/4/7/8/9 Table 12. Pin Descriptions (Continued) Pin Name Memory Interface (Continued) DDR_VREF DDR_VSSR Asynchronous Memory Interface A1-3 D0-15/ND_D0-15/ATAPI_D0-15 AMS0–3 ABE0 /ND_CLE ABE1/ND_ALE AOE/NR_ADV ARE AWE ATAPI Controller Pins ATAPI_PDIAG 9 High Speed USB OTG Pins USB_DP USB_DM USB_XI USB_XO 10 USB_ID USB_VBUS USB_VREF ...
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... This pin should always be enabled as bus request in software and pulled HIGH to enable the Async access. 9 For the ADSP-BF542/4/7/8/9, the unused USB pins should be terminated as follows: USB_DP --> GND; USB_DM -->GND; USB_XTALIN --> GND; USB_XTALOUT --> NC (No Connect); USB_ID --> VSS; USB_VREF --> NC; USB_RSET --> NC; USB_VBUS --> VSS; VDDUSB --> VDDEXT 10 In the case that USB is used in device mode only, the USB_ID pin should be either pulled HIGH or left unconnected ...
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... VDDVR must always be connected. If the internal voltage regulator is not being used, this pin may be connected to VDDEXT. Otherwise it should be powered according to this specification. 7 The ADSP-BF542/4/7/8/9 processor is 3.3 V tolerant (always accepts up to 3.6 V maximum V because V (maximum) approximately equals V OH PF15–0, PG15–0, PH13–0, PI15–0, PJ14–0) and input only pins (ATAPI_PDIAG, USB_ID, TCK, TDI, TMS, TRST, CLKIN, RESET, NMI, and BMODE3–0). ...
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... Parameter value applies to CLKIN pin only. 10 Parameter value applies to DA0–12, DBA0–1, DQ0–15, DQS0–1, DQM0–1, DCLK1–2, DCLK1–2, DCS0–1, DCLKE, DRAS, DCAS, and DWE pins only. 11 Certain ADSP-BF542/4/7/8/9 processor pins are 5.0 V tolerant (accept up to 5.5 V maximum depends on the input V , because V ...
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... ADSP-BF542/4/7/8/9 ELECTRICAL CHARACTERISTICS Parameter V High Level Output Voltage for 3. I/O High Level Output Voltage for 2.5V 1 I/O V High Level Output Voltage OHDDR High Level Output Voltage for 2 Mobile DDR V Low Level Output Voltage for 3. I/O Low Level Output Voltage for 2.5V 1 I/O V Low Level Output Voltage ...
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... C 1 Transient Voltage and Table 14 provides Table 14. Package Information Brand Key 82 vvvvvv.x-q n.n yyww Rev. PrG | Page December 2007 ADSP-BF542/4/7/8/9 Description Temperature Range Package Type RoHS Compliant part See Ordering Guide Assembly Lot Code Silicon Revision Date Code ...
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... TIMING SPECIFICATIONS Table 15, Table 16, Table 17, and Table 18 requirements for the ADSP-BF542/4/7/8/9 processor clocks. Take care in selecting MSEL, SSEL, and CSEL ratios so as not to exceed the maximum core clock and system clock. Clock Signals Table 15. System Clock Requirements Parameter Condition = 3 ≥ TBD ...
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... Guide” on page 82. It stands for the Maximum allowed CCLK frequency CKIN t CKINL CKINH t WRST Figure 9. Clock and Reset Timing Rev. PrG | Page December 2007 ADSP-BF542/4/7/8/9 Minimum Maximum 50 Speed Grade = minimum and the maximum DDINT Minimum Maximum 20.0 100.0 8.0 8 ...
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... ADSP-BF542/4/7/8/9 Table 21. Clock Out Timing Parameter Switching Characteristics 1 t CLKOUT Period SCLK t CLKOUT Width High SCLKH t CLKOUT Width Low SCLKL 1 The t value is the inverse of the f specification. Reduced supply voltages affect the best-case value of TBD ns listed here. SCLK SCLK CLKOUT t SCLK Figure 10. CLKOUT Interface Timing Rev ...
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... AOE ARE ARDY DATA15–0 Figure 11. Asynchronous Memory Read Cycle Timing with Synchronous ARDY and Figure PROGRAMMED READ ACCESS 4 CYCLES BE, ADDRESS SARDY t HARDY Rev. PrG | Page December 2007 ADSP-BF542/4/7/8/9 Min Max 2.1 0.8 4.0 0.0 6.0 0.8 HOLD 1 CYCLE ACCESS EXTENDED 3 CYCLES HARDY t t ...
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... ADSP-BF542/4/7/8/9 Table 23. Asynchronous Memory Read Cycle Timing with Asynchronous ARDY Parameter Timing Requirements t DATA15–0 Setup Before CLKOUT SDAT t DATA15–0 Hold After CLKOUT HDAT t ARDY Negated Delay from AMSx Asserted DANR t ARDY Asserted Hold After ARE Negated HAA t Output Delay After CLKOUT ...
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... Figure 13. Asynchronous Memory Write Cycle Timing with Synchronous ARDY and Figure ACCESS HOLD PROGRAMMED WRITE EXTENDED 1 CYCLE ACCESS 2 CYCLES 1 CYCLE BE, ADDRESS SARDY t t HARDY HARDY WRITE DATA Rev. PrG | Page December 2007 ADSP-BF542/4/7/8/9 Min Max 4.0 0.0 6.0 1.0 6.0 0 DDAT Unit ...
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... ADSP-BF542/4/7/8/9 Table 25. Asynchronous Memory Write Cycle Timing with Asynchronous ARDY Parameter Timing Requirements t ARDY Negated Delay from AMSx Asserted DANR t ARDY Asserted Hold After ARE Negated HAA Switching Characteristics t DATA15–0 Disable After CLKOUT DDAT t DATA15–0 Enable After CLKOUT ENDAT ...
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... Address and Control output tAS SETUP time relative to clock, CK Address and Control output tAH HOLD time relative to clock, CK TBD TBD nominal 2.5V DDDDR nominal 1.8 V DDDDR Rev. PrG | Page December 2007 ADSP-BF542/4/7/8/9 Minimum Maximum Unit TBD TBD ns TBD TBD ns 0.90 ns 2.50 ns TBD ...
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... ADSP-BF542/4/7/8/9 t DQSCK (MAX) t DQSCK (Min (MAX (MIN) t RPRE DQS DQ15-0 t DQSQ t DQSQ Figure 15. DDR SDRAM Controller Input AC Timing Rev. PrG | Page December 2007 Preliminary Technical Data t RPST ...
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... Address and Control output tAS SETUP time relative to clock, CK Address and Control output tAH HOLD time relative to clock, CK TBD TBD nominal 2.5V DDDDR nominal 1.8V DDDDR Rev. PrG | Page December 2007 ADSP-BF542/4/7/8/9 Minimum Maximum Unit 7.50 ns TBD TBD tCK 0.90 ns 0.90 ns TBD tCK ...
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... ADSP-BF542/4/7/8/9 CK DQS DQ/ ADDR CTL DSH t DSS t DQSS t DQSL t WPRE Figure 16. DDR SDRAM Controller Output AC Timing Rev. PrG | Page December 2007 Preliminary Technical Data t DQSH t WPST ...
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... EBH CLKOUT BR AMSx ADDR19-1 ABE1-0 ARE BG BGH Figure 17. External Port Bus Request and Grant Cycle Timing with Synchronous BR and Figure Rev. PrG | Page December 2007 ADSP-BF542/4/7/8/9 Min Max 4.0 0.0 4.5 4.5 3.6 3.6 3.6 3 DBG EBG t t DBH ...
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... ADSP-BF542/4/7/8/9 Table 31. External Port Bus Request and Grant Cycle Timing with Asynchronous BR Parameter Timing Requirements t BR Pulsewidth WBR Switching Characteristics t CLKOUT Low to xMS, Address, and RD/WR disable SD t CLKOUT Low to AMSx, Address, and ARE/AWE enable SE t CLKOUT High to BG High Setup DBG ...
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... DFSPE t Internal Frame Sync Hold After PPI_CLK HOFSPE t Transmit Data Delay After PPI_CLK DDTPE t Transmit Data Hold After PPI_CLK HDTPE Figure 19. Enhanced Parallel Peripheral Interface Timing Rev. PrG | Page December 2007 ADSP-BF542/4/7/8/9 Minimum Maximum Unit TBD ns TBD ns TBD ns TBD ns TBD ...
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... ADSP-BF542/4/7/8/9 Serial Ports Timing Table 33 through Table 36 on Page 51 and through Figure 22 on Page 54 describe Serial Port operations. Table 33. Serial Ports—External Clock Parameter Timing Requirements t TFS/RFS Setup Before TSCLK/RSCLK (externally generated TFS/RFS) SFSE t TFS/RFS Hold After TSCLK/RSCLK (externally generated TFS/RFS) ...
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... MCE = 1, TFS enable and TFS valid follow t DTENLFS 2 If external RFS/TFS setup to RSCLK/TSCLK > t SCLKE and t . DDTLFSE /2, then t and t apply; otherwise t DDTE/I DTENE/I DDTLFSE Rev. PrG | Page December 2007 ADSP-BF542/4/7/8/9 Min Max 0 10.0 –2.0 3.0 Min Max 1, 2 10.0 0 and t apply. DTENLFS Unit ...
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... ADSP-BF542/4/7/8/9 DATA RECEIVE- INTERNAL CLOCK DRIVE EDGE t SCLKIW RSCLK t DFSE t t HOFSE SFSI RFS t SDRI DR NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RCLK OR TCLK CAN BE USED AS THE ACTIVE SAMPLING EDGE. DATA TRANSMIT- INTERNAL CLOCK DRIVE EDGE t SCLKIW TSCLK t DFSI t t HOFSI ...
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... DTENLFS HDTE/I 1ST BIT t DDTLFSE DRIVE SAMPLE DRIVE t SFSE DTENLFS HDTE/I 1ST BIT t DDTLFSE Figure 21. External Late Frame Sync (Frame Sync Setup < t Rev. PrG | Page December 2007 ADSP-BF542/4/7/8/9 t DDTE/I 2ND BIT t HOFSE /I t DDTE/I 2ND BIT /2) SCLKE ...
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... ADSP-BF542/4/7/8/9 EXTERNAL RFS WITH MCE = 1, MFD = 0 RSCLK RFS DT LATE EXTERNAL TFS TSCLK TFS DT DRIVE SAMPLE DRIVE t t SFSE/I HOFSE/I t DDTE DTENLSCK HDTE/I 1ST BIT t DDTLSCK DRIVE SAMPLE DRIVE t t SFSE/I HOFSE/I t DDTE DTENLSCK HDTE/I 1ST BIT t DDTLSCK Figure 22. External Late Frame Sync (Frame Sync Setup > t Rev ...
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... SPICLM SPICHM t t DDSPIDM HDSPIDM MSB t HSPIDM MSB VALID t DDSPIDM MSB t HSPIDM LSB VALID Figure 23. Serial Peripheral Interface (SPI) Port—Master Timing Rev. PrG | Page December 2007 ADSP-BF542/4/7/8/9 Minimum Maximum 7.5 –1.5 2t –1.5 SCLK 2t –1.5 SCLK 2t –1.5 SCLK 4t –1.5 SCLK 2t –1.5 ...
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... ADSP-BF542/4/7/8/9 Serial Peripheral Interface (SPI) Port—Slave Timing Table 38 and Figure 24 describe SPI port slave operations. Table 38. Serial Peripheral Interface (SPI) Port—Slave Timing Parameter Timing Requirements t Serial clock high period SPICHS t Serial clock low period SPICLS t Serial clock period SPICLK ...
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... UART TRANSMIT BIT SET BY PROGRAM; CLEARED BY WRITE TO TRANSMIT Figure 25. UART Ports—Receive and Transmit Timing t GPOD t WFI Figure 26. General-Purpose Port Timing Rev. PrG | Page December 2007 ADSP-BF542/4/7/8/9 UART RECEIVE BIT SET BY DATA STOP ; CLEARED BY FIFO READ Minimum Maximum SCLK ...
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... ADSP-BF542/4/7/8/9 Timer Cycle Timing Table 40 and Figure 27 describe timer expired operations. The input signal is asynchronous in “width capture mode” and “external clock mode” and has an absolute maximum input fre- quency of (f /2) MHz. SCLK Table 40. Timer Cycle Timing Parameter Timing Characteristics ...
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... Either a valid setup and hold time or a valid pulse width is sufficient. There is no need to resynchronize counter inputs. CLK OUT CUD/CDG/CZM Figure 28. ATA/ATAPI Controller Timing CIS CIH t WCOUNT Figure 29. Up/Down Counter/Rotary Encoder Timing Rev. PrG | Page December 2007 ADSP-BF542/4/7/8/9 Minimum Maximum Unit TBD ns TBD ns Minimum Maximum Unit ...
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... ADSP-BF542/4/7/8/9 SD/SDIO Controller Timing Table 43. SD/SDIO Controller Timing Parameter Timing Requirements TBD TBD Switching Characteristic TBD TBD MXVR Timing Table 44 and Table 45 describe the MXVR timing requirements. Table 44. MXVR Timing—MXI Center Frequency Requirements Parameter f MXI Center Frequency (256Fs) _256 MXI ...
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... TBD 1 8.7 sclk Data Delay 1 HADRDH SADRDL t t RDWH RDWL t DRDYRDL t RDYPRD t DRDHRDY t HDARWH t SDATRDY Figure 31. HOSTDP A/C- Host Read Cycle Rev. PrG | Page December 2007 ADSP-BF542/4/7/8/9 Maximum + t (ACK DRDHRDY t sclk Units ...
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... ADSP-BF542/4/7/8/9 HOSTDP A/C Timing- Host Write Cycle Table 47 describes the HOSTDP A/C Host Write Cycle timing requirements. Table 47. Host Write Cycle Timing Requirements Parameter Timing Requirements t HOST_ADDR/Host_CE Setup before Host_WR SADWRH t HOST_ADDR/Host_CE Hold after Host_WR HADWRH t Host_WR pulse width low WRWL t Host_WR pulse width high ...
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... DCLK0-1, DCLK0–1, DCS1–0, DCLKE, DRAS, DCAS, DWE, AMS3–0, ABE1–0, AOE, ARE, AWE, EMU, CLKOUT, CLKBUF, EXT_WAKE. TCK TMS TDI TDO SYSTEM INPUTS SYSTEM OUTPUTS TCK t t STAP HTAP t DTDO t HSYS t SSYS t DSYS Figure 33. JTAG Port Timing Rev. PrG | Page December 2007 ADSP-BF542/4/7/8/9 Minimum Maximum Unit TCK ...
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... ADSP-BF542/4/7/8/9 POWER DISSIPATION Total power dissipation has two components: one due to inter- nal circuitry (P ) and one due to the switching of external INT output drivers (P ). Table 50 through EXT power dissipation for internal circuitry (V See the ADSP-BF549 Blackfin Processor Hardware Reference for definitions of the various operating modes and for instructions on how to minimize system power ...
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... Choose ΔV first calculate t DECAY to be the difference between the ADSP-BF542/4/7/8/9 proces- sor’s output voltage and the input threshold for the device requiring the hold time. A typical ΔV will be 0 bus capacitance (per data line), and I ...
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... ADSP-BF542/4/7/8/9 In Table 54, airflow measurements comply with JEDEC stan- dards JESD51-2 and JESD51-6, and the junction-to-board measurement complies with JESD51-8. The junction-to-case measurement complies with MIL-STD-883 (Method 1012.1). All measurements use a 2S2P JEDEC test board. Table 54. Thermal Characteristics, 360-Ball PBGA ...
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... GND K10 J18 GND K11 J17 GND K12 J16 GND K13 G20 GND L7 H19 GND L8 F20 GND L9 Rev. PrG | Page December 2007 ADSP-BF542/4/7/8/9 Signal Ball No. GND L10 GND L11 GND L12 GND L13 GND L14 GND M6 GND M7 GND M8 GND M9 GND ...
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... ADSP-BF542/4/7/8/9 Table 55. 400-Ball CSP_BGA Ball Assignment (Alphabetically by Signal) (Continued) Signal Ball No. Signal MLF_P E4 PC5 MXI C2 PC6 MXO C1 PC7 NMI C11 PC8 PA0 U12 PC9 PA1 V12 PC10 PA2 W12 PC11 PA3 Y12 PC12 PA4 W11 PC13 PA5 V11 PD0 PA6 Y11 ...
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... G7 V T14 DDEXT G14 V T15 DDEXT H5 V T16 DDEXT DDINT DDINT M15 V G12 DDINT Rev. PrG | Page December 2007 ADSP-BF542/4/7/8/9 Signal Ball No. V G13 DDINT V J6 DDINT V J13 DDINT V L6 DDINT V L15 DDINT V P6 DDINT V P7 DDINT V P14 ...
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... ADSP-BF542/4/7/8/9 Table 56 lists the CSP_BGA package by ball number for the ADSP-BF549. Table 55 on Page 67 lists the CSP_BGA package by signal. Table 56. 400-Ball CSP_BGA Ball Assignment (Numerically by Ball Number) Ball No. Signal Ball No. A1 GND PI0 C3 A4 PI2 C4 A5 PI4 C5 A6 PI6 ...
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... GND P14 V V P15 V DDEXT PJ2 P16 PG12 PJ11 P17 PJ9 EXT_WAKE P18 PJ6 DQ1 P19 ATAPI_PDIAG DDR_VREF P20 PJ12 Rev. PrG | Page December 2007 ADSP-BF542/4/7/8/9 Ball No. Signal R1 PD2 R2 PD3 R3 PD5 R4 PD7 R5 EMU DDEXT R6 V DDEXT R7 V DDEXT R8 V DDEXT ...
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... ADSP-BF542/4/7/8/9 Table 56. 400-Ball CSP_BGA Ball Assignment (Numerically by Ball Number) (Continued) Ball No. Signal Ball No. U1 PD8 V1 U2 PD9 V2 U3 PD15 V3 U4 PD14 V4 U5 TMS V5 U6 PB3 V6 U7 PB10 V7 U8 GND DDINT U10 PA8 V10 U11 PA7 V11 U12 PA0 V12 ...
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... GND N15 U25 GND P11 T25 GND P12 R26 GND P13 T26 GND P14 U26 GND P15 Rev. PrG | Page December 2007 ADSP-BF542/4/7/8/9 Signal Ball No. GND R12 GND R13 GND R14 GND R15 GND T12 GND T13 GND T14 GND ...
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... ADSP-BF542/4/7/8/9 Table 57. 360-Ball PBGA Ball Assignment (Alphabetically by Signal) (Continued) Signal Ball No. Signal PA5 AF11 PC10 PA6 AE10 PC11 PA7 AF10 PC12 PA8 AE9 PC13 PA9 AF9 PD0 PA10 AE8 PD1 PA11 AF8 PD2 PA12 AE7 PD3 PA13 AF7 PD4 PA14 AE6 ...
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... V R9 DDEXT K10 V T10 DDEXT K11 V T11 DDEXT K12 V U10 DDEXT K13 V U11 DDEXT K14 V K15 DDINT Rev. PrG | Page December 2007 ADSP-BF542/4/7/8/9 Signal Ball No. V K17 DDINT V L16 DDINT V L17 DDINT V M16 DDINT V M17 DDINT V M18 DDINT V N17 DDINT ...
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... ADSP-BF542/4/7/8/9 Table 58 lists the 360-Ball PBGA package by ball number for the ADSP-BF549. Table 59 on Page 81 lists the 360-Ball PBGA package by signal. Table 58. 360-Ball PBGA Ball Assignment (Numerically by Ball Number) Ball No. Signal Ball No. A1 GND B15 A2 A1 B16 A3 A3 B17 A4 PH9 B18 ...
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... AC1 PB3 VDDDDR AC2 PB4 VDDDDR AC3 PG4 PJ7 AC4 GND DQ6 AC23 GND DQ10 AC24 PE6 Rev. PrG | Page December 2007 ADSP-BF542/4/7/8/9 Ball No. Signal AC25 DQ0 AC26 DCS1 AD1 PB6 AD2 PB5 AD3 GND AD4 PB0 AD5 PB1 AD6 ...
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... ADSP-BF542/4/7/8/9 Table 58. 360-Ball PBGA Ball Assignment (Numerically by Ball Number) (Continued) Ball No. Signal Ball No. AE13 PA0 AE24 AE14 PC8 AE25 AE15 PC10 AE26 AE16 PC12 AF1 AE17 PH3 AF2 AE18 PG10 AF3 AE19 PG8 AF4 AE20 PG6 AF5 AE21 PG5 AF6 AE22 ...
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... 0.12 MAX COPLANARITY 0.50 BALL DIAMETER 0.45 0. CSP_BGA (Chip Scale Package Ball Grid Array) (BC-400) Rev. PrG | Page December 2007 ADSP-BF542/4/7/8/9 15.20 BSC SQ A1 BALL BOTTOM VIEW 0.28 MIN SEATING PLANE DETAIL A ...
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... ADSP-BF542/4/7/8/9 Dimensions for the 360-ball PBGA 27 mm Figure 40 are shown in millimeters. 27.20 27.00 SQ 26.80 6.75 BSC A1 BALL PAD CORNER TOP VIEW 2.40 2.28 2. package in 360-Ball Plastic Ball Grid Array [PBGA] (B-360-1) Dimensions shown in millimeters 24.20 24.00 SQ 23.80 25.00 BSC SQ 1.00 BSC 1.00 REF DETAIL A 0.66 0.61 0.56 0.50 NOM 0.45 MIN COMPLIANT TO JEDEC STANDARDS MS-034-AAL-1 Figure 40. 360-Ball PBGA (B-360-1) Rev ...
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... Table 59. BGA Data for Use with Surface Mount Design Package 400-Ball CSP_BGA (Chip Scale Package Ball Grid Array) BC-400 Solder Mask Defined 360-Ball PBGA (B-360-1) Ball Attach Type Soldier Mask Defined Rev. PrG | Page December 2007 ADSP-BF542/4/7/8/9 Solder Mask Opening Ball Pad Size 0.40 mm diameter 0.50 mm diameter 0.43 mm diameter 0.56 mm diameter ...
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... ADSP-BF548BBCZ-5X - ADSP-BF547BBCZ-5X - ADSP-BF544BBCZ-5X - ADSP-BF542BBCZ-5X - © 2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. PR06512-0-12/07(PrG) Speed Grade Operating Voltage (Nominal) Package Description Package Option ...