ADSP-BF542 AD [Analog Devices], ADSP-BF542 Datasheet - Page 61

• Manufacturer Part Number: ADSP-BF542
• Description: Embedded Processor
• Manufacturer: AD [Analog Devices]

Preliminary Technical Data
HOSTDP A/C Timing- Host Read Cycle
Table 46
requirements.
Table 46. Host Read Cycle Timing Requirements
Parameter
Timing Requirements
t
t
t
t
t
Switching Characteristics
t
t
t
t
SADRDL
HADRDH
RDWL
RDWH
DRDHRDY
SDATRDY
DRDYRDL
RDYPRD
HDARWH
describe the HOSTDP A/C Host Read Cycle timing
HOST_ADDR and Host_CE Setup before Host_RD assertion 1.5 * t
HOST_ADDR and Host_CE Hold after Host_RD assertion
Host_RD pulse width low
Host_RD pulse width high
Host_RD de-assertion delay after Host_ACK de-assertion
Data valid after Host_ACK assertion
Host_ACK assertion delay after Host_RD
Host_ACK low pulse-width for Read access
Data disable after Host_RD
HOST_ADDR
HOST_D15-0
HOST_ACK
HOST_CE
HOST_RD
t
DRDYRDL
Rev. PrG | Page 61 of 82 | December 2007
Figure 31. HOSTDP A/C- Host Read Cycle
t
SDATRDY
t
SADRDL
t
t
RDYPRD
RDWL
t
DRDHRDY
Minimum
2.5
t
mode)
1.5 * t
2 * t
TBD
1.5 * t
Data Delay
1.0
DRDYRDL
t
HDARWH
sclk
sclk
+ t
sclk
sclk
t
HADRDH
RDYPRD
+ 8.7 (INT mode)
+ 8.7
t
RDWH
+ t
DRDHRDY
(ACK
ADSP-BF542/4/7/8/9
Maximum
t
sclk
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns