ADSP-BF542 AD [Analog Devices], ADSP-BF542 Datasheet - Page 55

• Manufacturer Part Number: ADSP-BF542
• Description: Embedded Processor
• Manufacturer: AD [Analog Devices]

Preliminary Technical Data
Serial Peripheral Interface (SPI) Port—Master Timing
Table 37
Table 37. Serial Peripheral Interface (SPI) Port—Master Timing
Parameter
Timing Requirements
t
Switching Characteristics
t
t
t
t
t
t
t
t
t
SSPIDM
SDSCIM
SPICHM
SPICLM
SPICLK
HDSM
SPITDM
DDSPIDM
HDSPIDM
HSPIDM
and
CPHA=1
CPHA=0
Figure 23
(OUTPUT)
(INPUT)
(INPUT)
(OUTPUT)
(OUTPUT)
(CPOL = 0)
(CPOL = 1)
SPISELx
(OUTPUT)
(OUTPUT)
MISO
MISO
MOSI
MOSI
SCK
SCK
Data input valid to SCK edge (data input setup)
SCK sampling edge to data input invalid
SPISELx low to first SCK edge (x=0 or 1)
Serial clock high period
Serial clock low period
Serial clock period
Last SCK edge to SPISELx high (x=0 or 1)
Sequential transfer delay
SCK edge to data out valid (data out delay)
SCK edge to data out invalid (data out hold)
describe SPI port master operations.
t
SSPIDM
t
SDSCIM
MSB VALID
t
SSPIDM
MSB
t
t
SPICHM
SPICLM
MSB VALID
Figure 23. Serial Peripheral Interface (SPI) Port—Master Timing
t
HSPIDM
Rev. PrG | Page 55 of 82 | December 2007
t
t
t
DDSPIDM
MSB
SPICLM
SPICHM
t
HSPIDM
t
DDSPIDM
t
HDSPIDM
LSB VALID
t
t
SSPIDM
SPICLK
t
HDSPIDM
LSB VALID
LSB
t
HDSM
LSB
t
HSPIDM
ADSP-BF542/4/7/8/9
Minimum
7.5
–1.5
2t
2t
2t
4t
2t
2t
0
–1.0
t
SCLK
SCLK
SCLK
SCLK
SCLK
SCLK
SPITDM
–1.5
–1.5
–1.5
–1.5
–1.5
–1.5
Maximum
6
4.0
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns