ADSP-BF542 AD [Analog Devices], ADSP-BF542 Datasheet - Page 41

• Manufacturer Part Number: ADSP-BF542
• Description: Embedded Processor
• Manufacturer: AD [Analog Devices]

Preliminary Technical Data
Asynchronous Memory Write Cycle Timing
Table 24
on Page 42
tions for synchronous and for asynchronous ARDY.
Table 24. Asynchronous Memory Write Cycle Timing with Synchronous ARDY
1
Parameter
Timing Requirements
t
t
Switching Characteristics
t
t
t
t
Output pins include AMS3–0, ABE1–0, ADDR19–1, DATA15–0, AOE, AWE.
SARDY
HARDY
DDAT
ENDAT
DO
HO
and
ADDR19–1
DATA15–0
CLKOUT
describe asynchronous memory write cycle opera-
ABE1–0
AMSx
ARDY
Table 25 on Page 42
AWE
ARDY Setup Before the Falling Edge of CLKOUT
ARDY Hold After the Falling Edge of CLKOUT
DATA15–0 Disable After CLKOUT
DATA15–0 Enable After CLKOUT
Output Delay After CLKOUT
Output Hold After CLKOUT
2 CYCLES
t
END AT
SETUP
and
t
DO
t
t
Figure 13. Asynchronous Memory Write Cycle Timing with Synchronous ARDY
SARDY
DO
Figure 13
BE, ADDRESS
WRITE DATA
PROGRAMMED WRITE
ACCESS 2 CYCLES
1
1
and
Rev. PrG | Page 41 of 82 | December 2007
Figure 14
t
HARDY
t
SARDY
EXTENDED
ACCESS
1 CYCLE
t
HARDY
t
HO
1 CYCLE
HOLD
t
DDAT
t
HO
ADSP-BF542/4/7/8/9
Min
4.0
0.0
1.0
0.8
Max
6.0
6.0
Unit
ns
ns
ns
ns
ns
ns