ADSP-BF542 AD [Analog Devices], ADSP-BF542 Datasheet - Page 12

• Manufacturer Part Number: ADSP-BF542
• Description: Embedded Processor
• Manufacturer: AD [Analog Devices]

ADSP-BF542/4/7/8/9
Connect RTC pins RTXI and RTXO with external components
as shown in
WATCHDOG TIMER
The ADSP-BF542/4/7/8/9 processor includes a 32-bit timer that
can be used to implement a software watchdog function. A soft-
ware watchdog can improve system availability by forcing the
processor to a known state through generation of a hardware
reset, non-maskable interrupt (NMI), or general-purpose inter-
rupt, if the timer expires before being reset by software. The
programmer initializes the count value of the timer, enables the
appropriate interrupt, then enables the timer. Thereafter, the
software must reload the counter before it counts to zero from
the programmed value. This protects the system from remain-
ing in an unknown state where software, which would normally
reset the timer, has stopped running due to an external noise
condition or software error.
If configured to generate a hardware reset, the watchdog timer
resets both the core and the ADSP-BF542/4/7/8/9 processor
peripherals. After a reset, software can determine if the watch-
dog was the source of the hardware reset by interrogating a
status bit in the watchdog timer control register.
The timer is clocked by the system clock (SCLK), at a maximum
frequency of f
TIMERS
There are up to two timer units in the ADSP-BF542/4/7/8/9
processors. One unit provides eight general-purpose program-
mable timers and the other unit provides three. Each timer has
an external pin that can be configured either as a Pulse Width
Modulator (PWM) or timer output, as an input to clock the
timer, or as a mechanism for measuring pulse widths and peri-
ods of external events. These timers can be synchronized to an
external clock input on the TMRx pins, an external clock
TMRCLK input pin, or to the internal SCLK.
SUGGESTED COMPONENTS:
ECLIPTEK EC38J (THROUGH-HOLE PACKAGE)
EPSON MC405 12 PF LOAD (SURFACE MOUNT PACKAGE)
C1 = 22 PF
C2 = 22 PF
R1 = 10 M
NOTE: C1 AND C2 ARE SPECIFIC TO CRYSTAL SPECIFIED FOR X1.
CONTACT CRYSTAL MANUFACTURER FOR DETAILS. C1 AND C2
SPECIFICATIONS ASSUME BOARD TRACE CAPACITANCE OF 3 PF.
Figure
C1
SCLK
RTXI
Figure 4. External Components for RTC
.
4.
R1
X1
C2
RTXO
Rev. PrG | Page 12 of 82 | December 2007
The timer units can be used in conjunction with the two UARTs
and the CAN controller to measure the width of the pulses in
the data stream to provide a software auto-baud detect function
for the respective serial channels.
The timers can generate interrupts to the processor core provid-
ing periodic events for synchronization, either to the system
clock or to a count of external signals.
In addition to the general-purpose programmable timers,
another timer is also provided by the processor core. This extra
timer is clocked by the internal processor clock and is typically
used as a system tick clock for generation of operating system
periodic interrupts.
UP/DOWN COUNTER AND THUMBWHEEL
INTERFACE
A 32-bit up/down counter is provided that can sense 2-bit
quadrature or binary codes as typically emitted by industrial
drives or manual thumb wheels. The counter can also operate in
general-purpose up/down count modes. Then, count direction
is either controlled by a level-sensitive input pin or by two edge
detectors.
A third input can provide flexible zero marker support and can
alternatively be used to input the push-button signal of thumb
wheels. All three pins have a programmable debouncing circuit.
An internal signal forwarded to the timer unit enables one timer
to measure the intervals between count events. Boundary regis-
ters enable auto-zero operation or simple system warning by
interrupts when programmable count values are exceeded.
SERIAL PORTS (SPORTS)
The ADSP-BF542/4/7/8/9 processor incorporates up to four
dual-channel synchronous serial ports (SPORT0, SPORT1,
SPORT2, SPORT3) for serial and multiprocessor communica-
tions. The SPORTs support the following features:
• I
• Bidirectional operation. Each SPORT has two sets of inde-
• Buffered (8-deep) transmit and receive ports. Each port has
• Clocking. Each transmit and receive port can either use an
• Word length. Each SPORT supports serial data words from
• Framing. Each transmit and receive port can run with or
pendent transmit and receive pins, enabling eight channels
of I
a data register for transferring data words to and from
other processor components and shift registers for shifting
data in and out of the data registers.
external serial clock or generate its own, in frequencies
ranging from (f
3 to 32 bits in length, transferred most-significant-bit first
or least-significant-bit first.
without frame sync signals for each data word. Frame sync
signals can be generated internally or externally, active high
or low, and with either of two pulsewidths and early or late
frame sync.
2
S capable operation.
2
S stereo audio.
Preliminary Technical Data
SCLK
/131,070) Hz to (f
SCLK
/2) Hz.