ADSP-BF542 AD [Analog Devices], ADSP-BF542 Datasheet - Page 14

• Manufacturer Part Number: ADSP-BF542
• Description: Embedded Processor
• Manufacturer: AD [Analog Devices]

ADSP-BF542/4/7/8/9
sion of the ADSP-BF548 processor and the Automotive Grade
version of the ADSP-BF549 processor since those only have one
version each offered.
The ADSP-BF542/4/9 CAN controllers offer the following
features:
The electrical characteristics of each network connection are
very demanding so the CAN interface is typically divided into
two parts: a controller and a transceiver. This allows a single
controller to support different drivers and CAN networks. The
ADSP-BF542/4/9 CAN module represents only the controller
part of the interface. The controller interface supports connec-
tion to 3.3V high-speed, fault-tolerant, single-wire transceivers.
TWI CONTROLLER INTERFACE
The ADSP-BF542/4/7/8/9 processor includes up to two Two
Wire Interface (TWI) modules for providing a simple exchange
method of control data between multiple devices. The modules
are compatible with the widely used I
modules offer the capabilities of simultaneous Master and Slave
operation, support for both 7-bit addressing and multimedia
data arbitration. Each TWI interface uses two pins for transfer-
ring clock (SCL) and data (SDA) and supports the protocol at
speeds up to 400k bits/sec. The TWI interface pins are compati-
ble with 5 V logic levels.
Additionally, the ADSP-BF542/4/7/8/9 processor’s TWI mod-
ules are fully compatible with Serial Camera Control Bus
(SCCB) functionality for easier control of various CMOS cam-
era sensor devices.
PORTS
Because of their rich set of peripherals, the
ADSP-BF542/4/7/8/9 processors group the many peripheral
signals to ten ports—referred to as Port A to Port J. Most ports
contain 16 pins, a few have less. Many of the associated pins are
shared by multiple signals. The ports function as multiplexer
controls. Every port has its own set of memory-mapped regis-
ters to control port muxing and GPIO functionality.
General-Purpose I/O (GPIO)
Every pin in Port A to Port J can function as a GPIO pin result-
ing in a GPIO pin count of 154. While it is unlikely that all
GPIOs will be used in an application as all pins have multiple
• 32 mailboxes (8 receive only, 8 transmit only, 16 config-
• Dedicated acceptance masks for each mailbox.
• Additional data filtering on first two bytes.
• Support for both the standard (11-bit) and extended (29-
• Support for remote frames.
• Active or passive network support.
• CAN wakeup from hibernation mode (lowest static power
• Interrupts, including: TX complete, RX complete, error,
urable for receive or transmit).
bit) identifier (ID) message formats.
consumption mode).
global.
2
C bus standard. The TWI
Rev. PrG | Page 14 of 82 | December 2007
functions, the richness of GPIO functionality guarantees unre-
strictive pin usage. Every pin that is not used by any function
can be configured in GPIO mode on an individual basis.
After reset, all pins are in GPIO mode by default. Neither GPIO
output nor input drivers are active by default. Unused pins can
be left unconnected, therefore. GPIO data and direction control
registers provide flexible write-one-to-set and write-one-to-
clear mechanisms so that independent software threads do not
need to protect against each other because of expensive read-
modify-write operations when accessing the same port.
Pin Interrupts
Due to its large number of port pins, the ADSP-BF542/4/7/8/9
processors introduce a new scheme to manage pin interrupts.
Every port pin can request interrupts in either an edge-sensitive
or a level-sensitive manner with programmable polarity. Inter-
rupt functionality is decoupled from GPIO operation. Four
system-level interrupt channels (INT0, INT1, INT2 and INT3)
are reserved for this purpose. Each of these interrupt channels
can manage up to 32 interrupt pins. The assignment from pin to
interrupt is not performed at a pin by pin level. Rather, groups
of eight pins (half ports) can be flexibly assigned to interrupt
channels.
Every pin interrupt channel features a special set of 32-bit mem-
ory-mapped registers that enable half-port assignment and
interrupt management. This not only includes masking, identi-
fication, and clearing of requests, it also enables access to the
respective pin states and use of the interrupt latches regardless
of whether the interrupt is masked or not. Most control registers
feature multiple MMR address entries to write-one-to-set or
write-one-to-clear them individually.
PIXEL COMPOSITOR (PIXC)
The pixel compositor (PIXC) provides image overlay with
transparent-color support, alpha blending, and color space con-
version capability for output to TFT-LCDs as well as
NTSC/PAL video encoders. It provides all of the control to
allow two data streams from two separate data buffers to be
combined, blended, and converted into appropriate forms for
both LCD panels and digital video outputs. The main image
buffer provides the basic background image, which is presented
in the data stream. The overlay image buffer allows the user to
add multiple foreground text, graphics, or video objects on top
of the main image or video data stream.
ENHANCED PARALLEL PERIPHERAL INTERFACE
(EPPI)
The ADSP-BF542/4/7/8/9 processor provides up to three
Enhanced Parallel Peripheral Interfaces (EPPIs), supporting
data widths up to 24 bits wide. The EPPI supports direct con-
nection to TFT LCD panels, parallel A/D and D/A converters,
video encoders and decoders, image sensor modules and other
general purpose peripherals.
Preliminary Technical Data