ADSP-BF542 AD [Analog Devices], ADSP-BF542 Datasheet - Page 43

• Manufacturer Part Number: ADSP-BF542
• Description: Embedded Processor
• Manufacturer: AD [Analog Devices]

Preliminary Technical Data
DDR SDRAM Read Cycle Timing
Table 26. DDR SDRAM Read Cycle Timing, V
Mobile DDR SDRAM Read Cycle Timing
Table 27. Mobile DDR SDRAM Read Cycle Timing, V
Parameter
Timing Requirements
Access window of DQ to CK
Access window of DQS to CK
DQS-DQ skew, DQS to last DQ
valid
DQ-DQS hold, DQS to first DQ to
go invalid
DQS Read preamble
DQS Read postamble
Switching Characteristic
Clock Period
Address and Control output
SETUP time relative to clock, CK
Address and Control output
HOLD time relative to clock, CK
TBD
Parameter
Timing Requirements
Access window of DQ to CK
Access window of DQS to CK
DQS-DQ skew, DQS to last DQ
valid
DQ-DQS hold, DQS to first DQ to
go invalid
DQS Read preamble
DQS Read postamble
Switching Characteristic
Clock Period
Address and Control output
SETUP time relative to clock, CK
Address and Control output
HOLD time relative to clock, CK
TBD
Symbol
tAC
tDQSCK
tDQSQ
tQH
tRPRE
tRPST
tCK
tAS
tAH
TBD
Symbol
tAC
tDQSCK
tDQSQ
tQH
tRPRE
tRPST
tCK
tAS
tAH
TBD
Rev. PrG | Page 43 of 82 | December 2007
DDDDR
nominal 2.5V
DDDDR
nominal 1.8 V
Minimum
TBD
TBD
2.50
TBD
TBD
7.50
TBD
TBD
Minimum
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
ADSP-BF542/4/7/8/9
Maximum
TBD
TBD
0.90
TBD
Maximum
TBD
TBD
TBD
Unit
ns
ns
ns
ns
tCK
tCK
ns
ns
ns
ns
Unit
ns
ns
ns
ns
tCK
tCK
ns
ns
ns
ns